From 77583eca73bb7f386d6466414e150794578326df Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Wed, 6 Apr 2022 17:43:50 -0500 Subject: initial commit --- resume.json | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 resume.json (limited to 'resume.json') diff --git a/resume.json b/resume.json new file mode 100644 index 0000000..ee21b6a --- /dev/null +++ b/resume.json @@ -0,0 +1,47 @@ +{ + "supermileage": { + "title" : "Ecoillini Supermileage", + "date" : "Aug 2021 - Present", + "adc" : "Programmed STM32 multi-channel ADC and combined it with CAN bus data to control PWM outputs.", + "design" : "Designed a Joulemeter capable of measuring current and reporting back using the CAN bus protocol.", + "test" : "Tested the functionality of the Joulemeter using a synthetic load along with a high current power supply.", + "can" : "Debugged the CAN bus with an oscilloscope to verify the baudrate and the transmitted data.", + "team" : "Worked with a small team to define the CAN messages as well as coordinate the data content and frequency", + "documentation" : "Documented all the code on a wiki that clarified all variables and explained how the code worked.", + "server" : "Running Openbsd with gitea on a server for the programming team and perform constant maintanence and new feature migrations.", + "workstation" : "Supporting a proxmox hypervisor server with multiple instances of Windows and Linux running on it for aerodynamic simulations." + }, + "python_scripting": { + "title" : "Resume generator", + "date" : "Mar 2022 - Present", + "webscrape" : "Designed a webscrape engine using Beautiful Soup to get job information from a job board page.", + "semanticsearch" : "Used Python's NLTK to do a keyboard search against a json of experiences to generate a resume.", + "latexconversion" : "Verified the relevance of those experiences to the job, and output the text into a latex file." + }, + "verilog_gpu": { + "title" : "Primitive Verilog GPU", + "date" : "Feb 2022 - Present", + "clock" : "Wrote a verilog module to drive clocks for a given LCD display based on the blanking times given.", + "spi" : "A separate module read SPI commands and drew lines and background colors based on the command given.", + "framebuf" : "Controlled an internal frame buffer which was copied over to the external frame buffer during blanking times.", + "locking" : "Ensured that no module was accessing memory at the same time using a locking system similar to chip enable.", + "simulation" : "Ran behavioral simulations using verilator before synthesizing tests and running verilator on gate level descriptions.", + "testing" : "Using a logic analyzer and oscilloscope to check all timings after formal verification of the verilog." + }, + "verilog_cpu": { + "title" : "Verilog RISCV Softcore", + "date" : "Aug 2021 - Dec 2021", + "cpu" : "Implemented a pipelined RISCVIM-Z (Integer operations) compliant softcore in Verilog.", + "dram" : "Designed DRAM controller to access a single DDR3L chip on the development board to use as main memory.", + "simulation" : "Verilog was simulated using Icarus, verified using verilog test benches, and compiled onto a Lattice ECP5.", + "fpu" : "Floating point extensions were implemented with a ALU that does all floating point arithmatic operations." + }, + + "linux_server": { + "title" : "Linux Server", + "date" : "Dec 2019 - Present", + "webservice": "Maintain a Linux Server which is running multiple network services such as Git, a website and other programs.", + "nginx": "Use a NGINX reverse proxy to send inbound traffic to the appropriate locally run service.", + "secure": "Secured the Linux server by maintaining a iptables firewall along with only allowing ssh authentication and disabling root login." + } +} -- cgit v1.2.3