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authorJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
committerJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
commitc1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch)
treebd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/hazard.v
parentd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff)
downloadriscv-processor-inorder-master.tar.gz
Added new riscv processor design into git repoHEADmaster
Diffstat (limited to 'verilog/hazard.v')
-rw-r--r--verilog/hazard.v33
1 files changed, 33 insertions, 0 deletions
diff --git a/verilog/hazard.v b/verilog/hazard.v
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+`default_nettype none
+`timescale 1ns/1ps
+
+module hazard
+(
+ input wire [4:0] r1addr_e, r2addr_e,
+ input wire [4:0] waddr_m, waddr_w, waddr_e,
+ input wire wr_reg_m, wr_reg_w,
+ output wire [1:0] r1forward_e, r2forward_e,
+
+ input wire [4:0] r1addr_d, r2addr_d,
+ input wire wb_mem_e,
+ output wire stall_f, stall_d, flush_e, flush_d,
+
+ input wire branch_pc
+);
+
+// Forwarding Logic
+assign r1forward_e = r1addr_e != 5'b0 ? (r1addr_e == waddr_m ? {1'b0, wr_reg_m} : (r1addr_e == waddr_w ? {wr_reg_w, 1'b0} : 2'b00)) : 2'b00;
+assign r2forward_e = r2addr_e != 5'b0 ? (r2addr_e == waddr_m ? {1'b0, wr_reg_m} : (r2addr_e == waddr_w ? {wr_reg_w, 1'b0} : 2'b00)) : 2'b00;
+
+// Load Hazard Logic
+// TODO: Incoporate wb_pc_e into the calculations
+// so that if pc is being written back pipeline not stalled
+wire load_hazard = (waddr_e != 0) & ((r1addr_d == waddr_e) | (r2addr_d == waddr_e)) & wb_mem_e;
+
+// Pipeline control outputs
+assign stall_f = load_hazard;
+assign stall_d = load_hazard;
+assign flush_e = load_hazard | branch_pc;
+assign flush_d = branch_pc;
+
+endmodule