1 files changed, 40 insertions, 0 deletions
diff --git a/verilog/alu/v2/alu2.v b/verilog/alu/v2/alu2.v
new file mode 100644
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+++ b/verilog/alu/v2/alu2.v
@@ -0,0 +1,40 @@
+`default_nettype none
+`timescale 1us/1ns
+
+`include "aluOp.vh"
+
+module alu2
+(
+input wire [31:0] in1,
+input wire[31:0] in2,
+input wire[3:0] op,
+output wire[31:0] out
+);
+
+
+wire [31:0] diff = in1 - in2;
+reg [31:0] result;
+
+always @ (*)
+begin
+	case (op)
+		`ADD: result = in1 + in2;
+		`SUB: result = diff;
+		`XOR: result = in1 ^ in2;
+		`OR: result = in1 | in2;
+		`AND: result = in1 & in2;
+		`SLL: result = in1 << in2;
+		`SRL: result = in1 >> in2;
+		`SLTU: result = (in1 < in2 ? 32'b1 : 32'b0);
+		`NONE: result = in1;
+		`SLT: result = (in1[31] == in2[31] ? (diff[31] == 1'b0 ? 32'b0 : 32'b1) : (in1[31] == 1'b1 ? 32'b1 : 32'b0) );
+		`SRA: result = (in1 >> in2) | (in1[31] == 1'b0 ? 32'b0 :
+			32'hFFFFFFFF << ((in2[4] ? 0 : 5'b10000) + (in2[3] ? 0 : 5'b01000) +
+			(in2[2] ? 0 : 5'b00100) + (in2[1] ? 0 : 5'b00010) + (in2[0] ? 0 : 5'b00001))
+		);
+		default: result = 32'b0;
+	endcase
+end
+
+assign out = result;
+endmodule