diff options
Diffstat (limited to 'verilog/alu/v3/tbalu.cpp')
-rw-r--r-- | verilog/alu/v3/tbalu.cpp | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/verilog/alu/v3/tbalu.cpp b/verilog/alu/v3/tbalu.cpp new file mode 100644 index 0000000..b3947f8 --- /dev/null +++ b/verilog/alu/v3/tbalu.cpp @@ -0,0 +1,45 @@ +#include <stdlib.h> +#include <iostream> +#include <verilated.h> +#include <verilated_vcd_c.h> +#include "Valu.h" +#include "aluOp.h" +#define OP SRA +#define OPSTR "SRA" +#define SIGN "SRA" +#define LOWER -10 +#define UPPER 0 + +vluint64_t sim_time = 0; + +int main(int argc, char** argv, char** env) { + Valu *dut = new Valu; + + Verilated::traceEverOn(true); + VerilatedVcdC *m_trace = new VerilatedVcdC; + dut->trace(m_trace, 5); + m_trace->open("waveform.vcd"); + + dut->op = OP; + for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + m_trace->close(); + delete dut; + exit(EXIT_SUCCESS); +} |