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Diffstat (limited to 'verilog/alu/v5/Makefile')
-rw-r--r-- | verilog/alu/v5/Makefile | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/verilog/alu/v5/Makefile b/verilog/alu/v5/Makefile new file mode 100644 index 0000000..bb659a4 --- /dev/null +++ b/verilog/alu/v5/Makefile @@ -0,0 +1,35 @@ +PROJ=alu5 +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean |