From d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 16 Apr 2022 23:00:55 -0500 Subject: Added pdfs and more alu stuff --- riscv-card.pdf | Bin 121074 -> 175554 bytes verilog/a.out | 202 ------- verilog/alu/alu.v | 26 + verilog/alu/aluOp.vh | 14 + verilog/alu/tbalu.v | 50 ++ verilog/alu_ops.vh | 14 - verilog/bench_alu.v | 23 - verilog/fpu/a.out | 1251 +++++------------------------------------- verilog/register/a.out | 66 +++ verilog/register/registers.v | 22 + verilog/riscv_alu.v | 39 -- 11 files changed, 310 insertions(+), 1397 deletions(-) delete mode 100755 verilog/a.out create mode 100644 verilog/alu/alu.v create mode 100644 verilog/alu/aluOp.vh create mode 100644 verilog/alu/tbalu.v delete mode 100644 verilog/alu_ops.vh delete mode 100644 verilog/bench_alu.v create mode 100755 verilog/register/a.out create mode 100644 verilog/register/registers.v delete mode 100644 verilog/riscv_alu.v diff --git a/riscv-card.pdf b/riscv-card.pdf index be17bed..2286ca6 100644 Binary files a/riscv-card.pdf and b/riscv-card.pdf differ diff --git a/verilog/a.out b/verilog/a.out deleted file mode 100755 index 77036bc..0000000 --- a/verilog/a.out +++ /dev/null @@ -1,202 +0,0 @@ -#! /usr/bin/vvp -:ivl_version "11.0 (stable)" "(v11_0)"; -:ivl_delay_selection "TYPICAL"; -:vpi_time_precision - 9; -:vpi_module "/usr/lib/ivl/system.vpi"; -:vpi_module "/usr/lib/ivl/vhdl_sys.vpi"; -:vpi_module "/usr/lib/ivl/vhdl_textio.vpi"; -:vpi_module "/usr/lib/ivl/v2005_math.vpi"; -:vpi_module "/usr/lib/ivl/va_math.vpi"; -S_0x5585f3becd70 .scope module, "bench_alu" "bench_alu" 2 6; - .timescale -6 -9; -v0x5585f3c3e500_0 .net "alu_out", 31 0, L_0x5585f3c3e890; 1 drivers -v0x5585f3c3e5e0_0 .var "input1", 31 0; -v0x5585f3c3e680_0 .var "input2", 31 0; -v0x5585f3c3e720_0 .var "op", 3 0; -S_0x5585f3becf00 .scope module, "alu0" "riscv_alu" 2 12, 3 1 0, S_0x5585f3becd70; - .timescale -6 -9; - .port_info 0 /INPUT 32 "alu_in_1"; - .port_info 1 /INPUT 32 "alu_in_2"; - .port_info 2 /INPUT 4 "alu_op_i"; - .port_info 3 /OUTPUT 32 "alu_output"; -L_0x5585f3c3e890 .functor BUFZ 32, v0x5585f3c3e3a0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; -v0x5585f3c29b30_0 .net/s "alu_in_1", 31 0, v0x5585f3c3e5e0_0; 1 drivers -v0x5585f3c3dff0_0 .net "alu_in_2", 31 0, v0x5585f3c3e680_0; 1 drivers -v0x5585f3c3e0d0_0 .net "alu_op_i", 3 0, v0x5585f3c3e720_0; 1 drivers -v0x5585f3c3e190_0 .net "alu_output", 31 0, L_0x5585f3c3e890; alias, 1 drivers -v0x5585f3c3e270_0 .net "sub_alu", 31 0, L_0x5585f3c3e7f0; 1 drivers -v0x5585f3c3e3a0_0 .var "tmp_out", 31 0; -E_0x5585f3c2a2f0 .event edge, v0x5585f3c3e0d0_0, v0x5585f3c29b30_0, v0x5585f3c3dff0_0, v0x5585f3c3e270_0; -L_0x5585f3c3e7f0 .arith/sub 32, v0x5585f3c3e5e0_0, v0x5585f3c3e680_0; - .scope S_0x5585f3becf00; -T_0 ; - %wait E_0x5585f3c2a2f0; - %load/vec4 v0x5585f3c3e0d0_0; - %dup/vec4; - %pushi/vec4 4, 0, 4; - %cmp/u; - %jmp/1 T_0.0, 6; - %dup/vec4; - %pushi/vec4 6, 0, 4; - %cmp/u; - %jmp/1 T_0.1, 6; - %dup/vec4; - %pushi/vec4 9, 0, 4; - %cmp/u; - %jmp/1 T_0.2, 6; - %dup/vec4; - %pushi/vec4 8, 0, 4; - %cmp/u; - %jmp/1 T_0.3, 6; - %dup/vec4; - %pushi/vec4 7, 0, 4; - %cmp/u; - %jmp/1 T_0.4, 6; - %dup/vec4; - %pushi/vec4 1, 0, 4; - %cmp/u; - %jmp/1 T_0.5, 6; - %dup/vec4; - %pushi/vec4 2, 0, 4; - %cmp/u; - %jmp/1 T_0.6, 6; - %dup/vec4; - %pushi/vec4 3, 0, 4; - %cmp/u; - %jmp/1 T_0.7, 6; - %dup/vec4; - %pushi/vec4 11, 0, 4; - %cmp/u; - %jmp/1 T_0.8, 6; - %dup/vec4; - %pushi/vec4 10, 0, 4; - %cmp/u; - %jmp/1 T_0.9, 6; - %load/vec4 v0x5585f3c29b30_0; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.0 ; - %load/vec4 v0x5585f3c29b30_0; - %load/vec4 v0x5585f3c3dff0_0; - %add; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.1 ; - %load/vec4 v0x5585f3c3e270_0; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.2 ; - %load/vec4 v0x5585f3c29b30_0; - %load/vec4 v0x5585f3c3dff0_0; - %xor; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.3 ; - %load/vec4 v0x5585f3c29b30_0; - %load/vec4 v0x5585f3c3dff0_0; - %or; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.4 ; - %load/vec4 v0x5585f3c29b30_0; - %load/vec4 v0x5585f3c3dff0_0; - %and; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.5 ; - %load/vec4 v0x5585f3c29b30_0; - %ix/getv 4, v0x5585f3c3dff0_0; - %shiftl 4; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.6 ; - %load/vec4 v0x5585f3c29b30_0; - %ix/getv 4, v0x5585f3c3dff0_0; - %shiftr 4; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.7 ; - %load/vec4 v0x5585f3c29b30_0; - %ix/getv 4, v0x5585f3c3dff0_0; - %shiftr/s 4; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.8 ; - %load/vec4 v0x5585f3c29b30_0; - %load/vec4 v0x5585f3c3dff0_0; - %cmp/u; - %flag_mov 8, 5; - %jmp/0 T_0.12, 8; - %pushi/vec4 1, 0, 32; - %jmp/1 T_0.13, 8; -T_0.12 ; End of true expr. - %pushi/vec4 0, 0, 32; - %jmp/0 T_0.13, 8; - ; End of false expr. - %blend; -T_0.13; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.11; -T_0.9 ; - %load/vec4 v0x5585f3c29b30_0; - %parti/s 1, 31, 6; - %load/vec4 v0x5585f3c3dff0_0; - %parti/s 1, 31, 6; - %cmp/ne; - %jmp/0xz T_0.14, 4; - %load/vec4 v0x5585f3c29b30_0; - %parti/s 1, 31, 6; - %flag_set/vec4 8; - %jmp/0 T_0.16, 8; - %pushi/vec4 1, 0, 32; - %jmp/1 T_0.17, 8; -T_0.16 ; End of true expr. - %pushi/vec4 0, 0, 32; - %jmp/0 T_0.17, 8; - ; End of false expr. - %blend; -T_0.17; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; - %jmp T_0.15; -T_0.14 ; - %load/vec4 v0x5585f3c3e270_0; - %parti/s 1, 31, 6; - %flag_set/vec4 8; - %jmp/0 T_0.18, 8; - %pushi/vec4 1, 0, 32; - %jmp/1 T_0.19, 8; -T_0.18 ; End of true expr. - %pushi/vec4 0, 0, 32; - %jmp/0 T_0.19, 8; - ; End of false expr. - %blend; -T_0.19; - %store/vec4 v0x5585f3c3e3a0_0, 0, 32; -T_0.15 ; - %jmp T_0.11; -T_0.11 ; - %pop/vec4 1; - %jmp T_0; - .thread T_0, $push; - .scope S_0x5585f3becd70; -T_1 ; - %pushi/vec4 11, 0, 4; - %store/vec4 v0x5585f3c3e720_0, 0, 4; - %pushi/vec4 10, 0, 32; - %store/vec4 v0x5585f3c3e5e0_0, 0, 32; - %pushi/vec4 13, 0, 32; - %store/vec4 v0x5585f3c3e680_0, 0, 32; - %delay 50000, 0; - %load/vec4 v0x5585f3c3e5e0_0; - %load/vec4 v0x5585f3c3e680_0; - %load/vec4 v0x5585f3c3e500_0; - %vpi_call 2 19 "$display", "\012ALU OP AND: %d %16b + %d %16b = %d %b", S<2,vec4,s32>, v0x5585f3c3e5e0_0, S<1,vec4,s32>, v0x5585f3c3e680_0, S<0,vec4,s32>, v0x5585f3c3e500_0 {3 0 0}; - %vpi_call 2 20 "$finish" {0 0 0}; - %end; - .thread T_1; -# The file index is used to find the file name in the following table. -:file_names 4; - "N/A"; - ""; - "bench_alu.v"; - "./riscv_alu.v"; diff --git a/verilog/alu/alu.v b/verilog/alu/alu.v new file mode 100644 index 0000000..3a4213a --- /dev/null +++ b/verilog/alu/alu.v @@ -0,0 +1,26 @@ +`include "aluOp.vh" + +module riscv_alu +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + + +wire diff = alu_in_1 - alu_in_2; +wire ones = 32'hFFFFFFFF; + +assign alu_output = alu_op_i == ADD ? alu_in_1 + alu_in_2 : + alu_op_i == SUB ? diff : + alu_op_i == XOR ? alu_in_1 ^ alu_in_2 : + alu_op_i == OR ? alu_in_1 | alu_in_2 : + alu_op_i == AND ? alu_in_1 & alu_in_2 : + alu_op_i == SLL ? alu_in_1 << alu_in_2 : + alu_op_i == SRL ? alu_in_1 >> alu_in_2 : + alu_op_i == SLT ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : + alu_op_i == NONE ? alu_in_1 : 32'b0 : + alu_op_i == SLTU ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 0 ? 0 : 1) : (alu_in_1[31] == 1 ? 1 : 0) ) : + alu_op_i == SRA ? alu_in_1[31] == 0 ? alu_in_1 >> alu_in_2 : ; +endmodule diff --git a/verilog/alu/aluOp.vh b/verilog/alu/aluOp.vh new file mode 100644 index 0000000..c67cd33 --- /dev/null +++ b/verilog/alu/aluOp.vh @@ -0,0 +1,14 @@ +`ifndef ALU_OP +`define ALU_OP +`define ADD 4'b0000 +`define SUB 4'b1000 +`define XOR 4'b0100 +`define OR 4'b0110 +`define AND 4'b0111 +`define SLL 4'b0001 +`define SRL 4'b0101 +`define SRA 4'b1101 +`define SLT 4'b0010 +`define SLTU 4'b0011 +`define NONE 4'h1111 +`endif diff --git a/verilog/alu/tbalu.v b/verilog/alu/tbalu.v new file mode 100644 index 0000000..7ffc8bf --- /dev/null +++ b/verilog/alu/tbalu.v @@ -0,0 +1,50 @@ +`timescale 1us/1ns + +`include "alu_ops.vh" +`include "alu.v" + +module tbalu; + +reg [31:0] in1,in2; +wire [31:0] out; +reg [3:0] op; + +alu alu0 (in1, in2,op, out); + +initial begin + in1=-32'b1; + in2=32'b1; + op=`ADD; + #5 + $display("\nPlus:\t\t %d %32b + %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SUB; + #5 + $display("\nMinus:\t\t %d %32b - %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`XOR; + #5 + $display("\nXor:\t\t %d %32b ^ %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`OR; + #5 + $display("\nOr:\t\t %d %32b | %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`AND; + #5 + $display("\nAnd:\t\t %d %32b & %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SLL; + #5 + $display("\nLeft Logical:\t %d %32b << %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SRL; + #5 + $display("\nRight Logical:\t %d %32b >> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SRA; + #5 + $display("\nRight Arith:\t %d %32b >>> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SLT; + #5 + $display("\nSet Less:\t %d %32b < %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SLTU; + #5 + $display("\nSet Less U:\t %d %32b < U %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + $finish; +end + +endmodule diff --git a/verilog/alu_ops.vh b/verilog/alu_ops.vh deleted file mode 100644 index 258e124..0000000 --- a/verilog/alu_ops.vh +++ /dev/null @@ -1,14 +0,0 @@ -`ifndef ALU_OP -`define ALU_OP -`define NONE 4'b0000 -`define SLL 4'b0001 -`define SRL 4'b0010 -`define SRA 4'b0011 -`define ADD 4'b0100 -`define SUB 4'b0110 -`define AND 4'b0111 -`define OR 4'b1000 -`define XOR 4'b1001 -`define SLTU 4'b1010 -`define SLT 4'b1011 -`endif diff --git a/verilog/bench_alu.v b/verilog/bench_alu.v deleted file mode 100644 index 9c0140c..0000000 --- a/verilog/bench_alu.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1us/1ns - -`include "riscv_alu.v" -`include "alu_ops.vh" - -module bench_alu; - -reg [3:0] op; -reg [31:0] input1, input2; -wire [31:0] alu_out; - -riscv_alu alu0 (input1, input2, op, alu_out); - -initial begin - op=`SLT; - input1=32'hA; - input2=32'hD; - #50 - $display("\nALU OP AND: %d %16b + %d %16b = %d %b", $signed(input1), input1, $signed(input2), input2, $signed(alu_out), alu_out); - $finish; -end - -endmodule diff --git a/verilog/fpu/a.out b/verilog/fpu/a.out index da37dbf..a1fd8c5 100755 --- a/verilog/fpu/a.out +++ b/verilog/fpu/a.out @@ -1,1147 +1,160 @@ #! /usr/bin/vvp :ivl_version "11.0 (stable)" "(v11_0)"; :ivl_delay_selection "TYPICAL"; -:vpi_time_precision - 9; +:vpi_time_precision + 0; :vpi_module "/usr/lib/ivl/system.vpi"; :vpi_module "/usr/lib/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/ivl/va_math.vpi"; -S_0x562fb3df3a70 .scope module, "fpu_bench" "fpu_bench" 2 5; - .timescale -6 -9; -v0x562fb3e81df0_0 .var "add", 0 0; -v0x562fb3e81eb0_0 .var "float1", 63 0; -v0x562fb3e81f70_0 .var "float2", 63 0; -v0x562fb3e82060_0 .var "float_out", 63 0; -v0x562fb3e82140_0 .net "fpu_output", 31 0, L_0x562fb3e9ac30; 1 drivers -v0x562fb3e82200_0 .var "input1", 31 0; -v0x562fb3e822d0_0 .var "input2", 31 0; -S_0x562fb3df2070 .scope module, "fpu0" "fpu_2" 2 12, 3 2 0, S_0x562fb3df3a70; - .timescale -6 -9; - .port_info 0 /INPUT 1 "add_not"; - .port_info 1 /INPUT 32 "a_in"; - .port_info 2 /INPUT 32 "b_in"; - .port_info 3 /OUTPUT 32 "out"; -L_0x562fb3e82650 .functor XOR 1, L_0x562fb3e82e50, L_0x562fb3e82ef0, C4<0>, C4<0>; -L_0x562fb3e830a0 .functor NOT 1, L_0x562fb3e82650, C4<0>, C4<0>, C4<0>; -L_0x562fb3e82f90 .functor NOT 24, L_0x562fb3e846b0, C4<000000000000000000000000>, C4<000000000000000000000000>, C4<000000000000000000000000>; -L_0x562fb3e94e70 .functor NOT 24, L_0x562fb3e84a30, C4<000000000000000000000000>, C4<000000000000000000000000>, C4<000000000000000000000000>; -L_0x562fb3e954f0 .functor NOT 25, L_0x562fb3e961a0, C4<0000000000000000000000000>, C4<0000000000000000000000000>, C4<0000000000000000000000000>; -L_0x562fb3e96330 .functor OR 1, L_0x562fb3e96a20, L_0x562fb3e830a0, C4<0>, C4<0>; -L_0x562fb3e96c30 .functor NOT 25, L_0x562fb3e96700, C4<0000000000000000000000000>, C4<0000000000000000000000000>, C4<0000000000000000000000000>; -L_0x562fb3e96d40 .functor OR 1, L_0x562fb3e973a0, L_0x562fb3e975f0, C4<0>, C4<0>; -L_0x562fb3e97780 .functor AND 1, v0x562fb3e81df0_0, L_0x562fb3e96d40, C4<1>, C4<1>; -L_0x562fb3e97b40 .functor XOR 1, L_0x562fb3e97840, L_0x562fb3e97aa0, C4<0>, C4<0>; -L_0x562fb3e97cb0 .functor XOR 1, L_0x562fb3e97b40, v0x562fb3e81df0_0, C4<0>, C4<0>; -L_0x562fb3e9a120 .functor AND 1, L_0x562fb3e99e30, L_0x562fb3e830a0, C4<1>, C4<1>; -L_0x562fb3e9a2f0 .functor AND 1, L_0x562fb3e9bc10, L_0x562fb3e830a0, C4<1>, C4<1>; -v0x562fb3e7ac90_0 .net *"_ivl_1", 7 0, L_0x562fb3e823a0; 1 drivers -v0x562fb3e7ad90_0 .net *"_ivl_100", 24 0, L_0x562fb3e95a70; 1 drivers -L_0x7f669afc91c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7ae70_0 .net *"_ivl_103", 0 0, L_0x7f669afc91c8; 1 drivers -v0x562fb3e7af30_0 .net *"_ivl_104", 24 0, L_0x562fb3e95b60; 1 drivers -L_0x7f669afc9210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7b010_0 .net *"_ivl_107", 0 0, L_0x7f669afc9210; 1 drivers -v0x562fb3e7b140_0 .net *"_ivl_110", 24 0, L_0x562fb3e95f40; 1 drivers -L_0x7f669afc9258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7b220_0 .net *"_ivl_113", 0 0, L_0x7f669afc9258; 1 drivers -v0x562fb3e7b300_0 .net *"_ivl_114", 24 0, L_0x562fb3e961a0; 1 drivers -L_0x7f669afc92a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7b3e0_0 .net *"_ivl_117", 0 0, L_0x7f669afc92a0; 1 drivers -v0x562fb3e7b4c0_0 .net *"_ivl_118", 24 0, L_0x562fb3e954f0; 1 drivers -v0x562fb3e7b5a0_0 .net *"_ivl_120", 24 0, L_0x562fb3e96290; 1 drivers -L_0x7f669afc92e8 .functor BUFT 1, C4<0000000000000000000000001>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7b680_0 .net/2u *"_ivl_122", 24 0, L_0x7f669afc92e8; 1 drivers -v0x562fb3e7b760_0 .net *"_ivl_129", 0 0, L_0x562fb3e96a20; 1 drivers -v0x562fb3e7b840_0 .net *"_ivl_13", 0 0, L_0x562fb3e82a80; 1 drivers -v0x562fb3e7b920_0 .net *"_ivl_130", 0 0, L_0x562fb3e96330; 1 drivers -v0x562fb3e7ba00_0 .net *"_ivl_132", 24 0, L_0x562fb3e96c30; 1 drivers -L_0x7f669afc9330 .functor BUFT 1, C4<0000000000000000000000001>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7bae0_0 .net/2u *"_ivl_134", 24 0, L_0x7f669afc9330; 1 drivers -v0x562fb3e7bbc0_0 .net *"_ivl_136", 24 0, L_0x562fb3e96ca0; 1 drivers -v0x562fb3e7bca0_0 .net *"_ivl_143", 0 0, L_0x562fb3e973a0; 1 drivers -v0x562fb3e7bd80_0 .net *"_ivl_145", 0 0, L_0x562fb3e975f0; 1 drivers -v0x562fb3e7be60_0 .net *"_ivl_146", 0 0, L_0x562fb3e96d40; 1 drivers -v0x562fb3e7bf40_0 .net *"_ivl_148", 0 0, L_0x562fb3e97780; 1 drivers -v0x562fb3e7c020_0 .net *"_ivl_15", 7 0, L_0x562fb3e82b70; 1 drivers -v0x562fb3e7c100_0 .net *"_ivl_151", 0 0, L_0x562fb3e97840; 1 drivers -v0x562fb3e7c1e0_0 .net *"_ivl_153", 0 0, L_0x562fb3e97aa0; 1 drivers -v0x562fb3e7c2c0_0 .net *"_ivl_154", 0 0, L_0x562fb3e97b40; 1 drivers -v0x562fb3e7c3a0_0 .net *"_ivl_156", 0 0, L_0x562fb3e97cb0; 1 drivers -v0x562fb3e7c480_0 .net *"_ivl_158", 0 0, L_0x562fb3e97db0; 1 drivers -L_0x7f669afc93c0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7c540_0 .net/2u *"_ivl_160", 1 0, L_0x7f669afc93c0; 1 drivers -L_0x7f669afc9408 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7c620_0 .net/2u *"_ivl_162", 1 0, L_0x7f669afc9408; 1 drivers -v0x562fb3e7c700_0 .net *"_ivl_164", 1 0, L_0x562fb3e98020; 1 drivers -v0x562fb3e7c7e0_0 .net *"_ivl_167", 0 0, L_0x562fb3e98160; 1 drivers -v0x562fb3e7c8c0_0 .net *"_ivl_168", 1 0, L_0x562fb3e983e0; 1 drivers -v0x562fb3e7c9a0_0 .net *"_ivl_17", 7 0, L_0x562fb3e82c60; 1 drivers -L_0x7f669afc9450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7ca80_0 .net *"_ivl_171", 0 0, L_0x7f669afc9450; 1 drivers -v0x562fb3e7cb60_0 .net *"_ivl_172", 1 0, L_0x562fb3e98520; 1 drivers -v0x562fb3e7cc40_0 .net *"_ivl_174", 0 0, L_0x562fb3e988a0; 1 drivers -v0x562fb3e7cd00_0 .net *"_ivl_177", 0 0, L_0x562fb3e98940; 1 drivers -v0x562fb3e7cde0_0 .net *"_ivl_178", 1 0, L_0x562fb3e98be0; 1 drivers -L_0x7f669afc9498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7cec0_0 .net *"_ivl_181", 0 0, L_0x7f669afc9498; 1 drivers -v0x562fb3e7cfa0_0 .net *"_ivl_183", 0 0, L_0x562fb3e98d20; 1 drivers -v0x562fb3e7d080_0 .net *"_ivl_184", 1 0, L_0x562fb3e98fd0; 1 drivers -L_0x7f669afc94e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7d160_0 .net *"_ivl_187", 0 0, L_0x7f669afc94e0; 1 drivers -v0x562fb3e7d240_0 .net *"_ivl_188", 1 0, L_0x562fb3e99110; 1 drivers -v0x562fb3e7d320_0 .net *"_ivl_190", 1 0, L_0x562fb3e994c0; 1 drivers -v0x562fb3e7d400_0 .net *"_ivl_193", 0 0, L_0x562fb3e99650; 1 drivers -v0x562fb3e7d4e0_0 .net *"_ivl_197", 0 0, L_0x562fb3e99970; 1 drivers -v0x562fb3e7d5c0_0 .net *"_ivl_198", 7 0, L_0x562fb3e99a60; 1 drivers -v0x562fb3e7d6a0_0 .net *"_ivl_200", 7 0, L_0x562fb3e99d90; 1 drivers -v0x562fb3e7d780_0 .net *"_ivl_203", 0 0, L_0x562fb3e99e30; 1 drivers -v0x562fb3e7d860_0 .net *"_ivl_204", 0 0, L_0x562fb3e9a120; 1 drivers -L_0x7f669afc9528 .functor BUFT 1, C4<00000001>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7d940_0 .net/2u *"_ivl_206", 7 0, L_0x7f669afc9528; 1 drivers -v0x562fb3e7da20_0 .net *"_ivl_208", 7 0, L_0x562fb3e9a250; 1 drivers -v0x562fb3e7db00_0 .net *"_ivl_21", 0 0, L_0x562fb3e82e50; 1 drivers -v0x562fb3e7dbe0_0 .net *"_ivl_210", 7 0, L_0x562fb3e9a3b0; 1 drivers -v0x562fb3e7dcc0_0 .net *"_ivl_212", 7 0, L_0x562fb3e9a740; 1 drivers -v0x562fb3e7dda0_0 .net *"_ivl_214", 7 0, L_0x562fb3e9a880; 1 drivers -v0x562fb3e7de80_0 .net *"_ivl_220", 22 0, L_0x562fb3e9adc0; 1 drivers -v0x562fb3e7df60_0 .net *"_ivl_222", 0 0, L_0x562fb3e9b0e0; 1 drivers -v0x562fb3e7e040_0 .net *"_ivl_224", 22 0, L_0x562fb3e9b210; 1 drivers -v0x562fb3e7e120_0 .net *"_ivl_226", 22 0, L_0x562fb3e9b540; 1 drivers -v0x562fb3e7e200_0 .net *"_ivl_227", 22 0, L_0x562fb3e9b5e0; 1 drivers -v0x562fb3e7e2e0_0 .net *"_ivl_229", 22 0, L_0x562fb3e9b9c0; 1 drivers -v0x562fb3e7e3c0_0 .net *"_ivl_23", 0 0, L_0x562fb3e82ef0; 1 drivers -v0x562fb3e7e4a0_0 .net *"_ivl_232", 0 0, L_0x562fb3e9bc10; 1 drivers -v0x562fb3e7e990_0 .net *"_ivl_233", 0 0, L_0x562fb3e9a2f0; 1 drivers -v0x562fb3e7ea70_0 .net *"_ivl_236", 22 0, L_0x562fb3e9bf60; 1 drivers -v0x562fb3e7eb50_0 .net *"_ivl_238", 22 0, L_0x562fb3e9c000; 1 drivers -v0x562fb3e7ec30_0 .net *"_ivl_24", 0 0, L_0x562fb3e82650; 1 drivers -v0x562fb3e7ed10_0 .net *"_ivl_240", 22 0, L_0x562fb3e9c360; 1 drivers -v0x562fb3e7edf0_0 .net *"_ivl_241", 22 0, L_0x562fb3e9c400; 1 drivers -v0x562fb3e7eed0_0 .net *"_ivl_243", 22 0, L_0x562fb3e9c810; 1 drivers -v0x562fb3e7efb0_0 .net *"_ivl_245", 22 0, L_0x562fb3e9c9a0; 1 drivers -v0x562fb3e7f090_0 .net *"_ivl_29", 7 0, L_0x562fb3e83160; 1 drivers -v0x562fb3e7f170_0 .net *"_ivl_3", 7 0, L_0x562fb3e824c0; 1 drivers -v0x562fb3e7f250_0 .net *"_ivl_31", 0 0, L_0x562fb3e83200; 1 drivers -L_0x7f669afc9018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7f310_0 .net/2u *"_ivl_32", 0 0, L_0x7f669afc9018; 1 drivers -v0x562fb3e7f3f0_0 .net *"_ivl_35", 22 0, L_0x562fb3e83370; 1 drivers -v0x562fb3e7f4d0_0 .net *"_ivl_36", 23 0, L_0x562fb3e83410; 1 drivers -L_0x7f669afc9060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7f5b0_0 .net/2u *"_ivl_38", 0 0, L_0x7f669afc9060; 1 drivers -v0x562fb3e7f690_0 .net *"_ivl_41", 22 0, L_0x562fb3e835e0; 1 drivers -v0x562fb3e7f770_0 .net *"_ivl_42", 23 0, L_0x562fb3e83680; 1 drivers -v0x562fb3e7f850_0 .net *"_ivl_47", 7 0, L_0x562fb3e83a20; 1 drivers -v0x562fb3e7f930_0 .net *"_ivl_49", 0 0, L_0x562fb3e837f0; 1 drivers -L_0x7f669afc90a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7f9f0_0 .net/2u *"_ivl_50", 0 0, L_0x7f669afc90a8; 1 drivers -v0x562fb3e7fad0_0 .net *"_ivl_53", 22 0, L_0x562fb3e83bc0; 1 drivers -v0x562fb3e7fbb0_0 .net *"_ivl_54", 23 0, L_0x562fb3e83d20; 1 drivers -L_0x7f669afc90f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7fc90_0 .net/2u *"_ivl_56", 0 0, L_0x7f669afc90f0; 1 drivers -v0x562fb3e7fd70_0 .net *"_ivl_59", 22 0, L_0x562fb3e83e90; 1 drivers -v0x562fb3e7fe50_0 .net *"_ivl_60", 23 0, L_0x562fb3e84000; 1 drivers -v0x562fb3e7ff30_0 .net *"_ivl_65", 0 0, L_0x562fb3e843e0; 1 drivers -v0x562fb3e80010_0 .net *"_ivl_66", 23 0, L_0x562fb3e84480; 1 drivers -v0x562fb3e800f0_0 .net *"_ivl_7", 7 0, L_0x562fb3e82760; 1 drivers -v0x562fb3e801d0_0 .net *"_ivl_71", 0 0, L_0x562fb3e847f0; 1 drivers -v0x562fb3e802b0_0 .net *"_ivl_72", 23 0, L_0x562fb3e84990; 1 drivers -v0x562fb3e80390_0 .net *"_ivl_77", 0 0, L_0x562fb3e84c80; 1 drivers -v0x562fb3e80470_0 .net *"_ivl_78", 23 0, L_0x562fb3e82f90; 1 drivers -L_0x7f669afc9138 .functor BUFT 1, C4<000000000000000000000001>, C4<0>, C4<0>, C4<0>; -v0x562fb3e80550_0 .net/2u *"_ivl_80", 23 0, L_0x7f669afc9138; 1 drivers -v0x562fb3e80630_0 .net *"_ivl_82", 23 0, L_0x562fb3e94dd0; 1 drivers -v0x562fb3e80710_0 .net *"_ivl_84", 23 0, L_0x562fb3e950a0; 1 drivers -v0x562fb3e807f0_0 .net *"_ivl_89", 0 0, L_0x562fb3e953b0; 1 drivers -v0x562fb3e808d0_0 .net *"_ivl_9", 7 0, L_0x562fb3e82830; 1 drivers -v0x562fb3e809b0_0 .net *"_ivl_90", 23 0, L_0x562fb3e94e70; 1 drivers -L_0x7f669afc9180 .functor BUFT 1, C4<000000000000000000000001>, C4<0>, C4<0>, C4<0>; -v0x562fb3e80a90_0 .net/2u *"_ivl_92", 23 0, L_0x7f669afc9180; 1 drivers -v0x562fb3e80b70_0 .net *"_ivl_94", 23 0, L_0x562fb3e95450; 1 drivers -v0x562fb3e80c50_0 .net *"_ivl_96", 23 0, L_0x562fb3e956f0; 1 drivers -v0x562fb3e80d30_0 .net "a_in", 31 0, v0x562fb3e82200_0; 1 drivers -v0x562fb3e80e10_0 .net "a_shft_sig", 23 0, L_0x562fb3e846b0; 1 drivers -v0x562fb3e80ef0_0 .net "a_sig", 23 0, L_0x562fb3e83890; 1 drivers -v0x562fb3e80fd0_0 .net "a_sign_sig", 23 0, L_0x562fb3e951e0; 1 drivers -v0x562fb3e810b0_0 .net "add_not", 0 0, v0x562fb3e81df0_0; 1 drivers -v0x562fb3e81170_0 .net "b_in", 31 0, v0x562fb3e822d0_0; 1 drivers -v0x562fb3e81250_0 .net "b_shft_sig", 23 0, L_0x562fb3e84a30; 1 drivers -v0x562fb3e81330_0 .net "b_sig", 23 0, L_0x562fb3e84170; 1 drivers -v0x562fb3e81410_0 .net "b_sign_sig", 23 0, L_0x562fb3e95830; 1 drivers -v0x562fb3e814f0_0 .net "diff", 7 0, L_0x562fb3e825b0; 1 drivers -v0x562fb3e815d0_0 .net "exp", 7 0, L_0x562fb3e82d00; 1 drivers -v0x562fb3e81690_0 .net "exp_diff", 7 0, L_0x562fb3e97260; 1 drivers -v0x562fb3e81730_0 .net "neg_diff", 7 0, L_0x562fb3e828d0; 1 drivers -v0x562fb3e817f0_0 .net "out", 31 0, L_0x562fb3e9ac30; alias, 1 drivers -v0x562fb3e818d0_0 .net "same_sign", 0 0, L_0x562fb3e830a0; 1 drivers -v0x562fb3e81990_0 .net "sig_diff", 24 0, L_0x562fb3e965c0; 1 drivers -v0x562fb3e81a70_0 .net "sig_diff_final", 24 0, v0x562fb3e7a780_0; 1 drivers -v0x562fb3e81b30_0 .net "sig_final", 24 0, L_0x562fb3e96fa0; 1 drivers -v0x562fb3e81bd0_0 .net "sig_op", 24 0, L_0x562fb3e96700; 1 drivers -v0x562fb3e81c90_0 .net "sig_sum", 24 0, L_0x562fb3e95e00; 1 drivers -L_0x562fb3e823a0 .part v0x562fb3e82200_0, 23, 8; -L_0x562fb3e824c0 .part v0x562fb3e822d0_0, 23, 8; -L_0x562fb3e825b0 .arith/sub 8, L_0x562fb3e823a0, L_0x562fb3e824c0; -L_0x562fb3e82760 .part v0x562fb3e822d0_0, 23, 8; -L_0x562fb3e82830 .part v0x562fb3e82200_0, 23, 8; -L_0x562fb3e828d0 .arith/sub 8, L_0x562fb3e82760, L_0x562fb3e82830; -L_0x562fb3e82a80 .part L_0x562fb3e825b0, 7, 1; -L_0x562fb3e82b70 .part v0x562fb3e822d0_0, 23, 8; -L_0x562fb3e82c60 .part v0x562fb3e82200_0, 23, 8; -L_0x562fb3e82d00 .functor MUXZ 8, L_0x562fb3e82c60, L_0x562fb3e82b70, L_0x562fb3e82a80, C4<>; -L_0x562fb3e82e50 .part v0x562fb3e82200_0, 31, 1; -L_0x562fb3e82ef0 .part v0x562fb3e822d0_0, 31, 1; -L_0x562fb3e83160 .part v0x562fb3e82200_0, 23, 8; -L_0x562fb3e83200 .reduce/or L_0x562fb3e83160; -L_0x562fb3e83370 .part v0x562fb3e82200_0, 0, 23; -L_0x562fb3e83410 .concat [ 23 1 0 0], L_0x562fb3e83370, L_0x7f669afc9018; -L_0x562fb3e835e0 .part v0x562fb3e82200_0, 0, 23; -L_0x562fb3e83680 .concat [ 23 1 0 0], L_0x562fb3e835e0, L_0x7f669afc9060; -L_0x562fb3e83890 .functor MUXZ 24, L_0x562fb3e83680, L_0x562fb3e83410, L_0x562fb3e83200, C4<>; -L_0x562fb3e83a20 .part v0x562fb3e822d0_0, 23, 8; -L_0x562fb3e837f0 .reduce/or L_0x562fb3e83a20; -L_0x562fb3e83bc0 .part v0x562fb3e822d0_0, 0, 23; -L_0x562fb3e83d20 .concat [ 23 1 0 0], L_0x562fb3e83bc0, L_0x7f669afc90a8; -L_0x562fb3e83e90 .part v0x562fb3e822d0_0, 0, 23; -L_0x562fb3e84000 .concat [ 23 1 0 0], L_0x562fb3e83e90, L_0x7f669afc90f0; -L_0x562fb3e84170 .functor MUXZ 24, L_0x562fb3e84000, L_0x562fb3e83d20, L_0x562fb3e837f0, C4<>; -L_0x562fb3e843e0 .part L_0x562fb3e825b0, 7, 1; -L_0x562fb3e84480 .shift/r 24, L_0x562fb3e83890, L_0x562fb3e828d0; -L_0x562fb3e846b0 .functor MUXZ 24, L_0x562fb3e83890, L_0x562fb3e84480, L_0x562fb3e843e0, C4<>; -L_0x562fb3e847f0 .part L_0x562fb3e825b0, 7, 1; -L_0x562fb3e84990 .shift/r 24, L_0x562fb3e84170, L_0x562fb3e825b0; -L_0x562fb3e84a30 .functor MUXZ 24, L_0x562fb3e84990, L_0x562fb3e84170, L_0x562fb3e847f0, C4<>; -L_0x562fb3e84c80 .part v0x562fb3e82200_0, 31, 1; -L_0x562fb3e94dd0 .arith/sum 24, L_0x562fb3e82f90, L_0x7f669afc9138; -L_0x562fb3e950a0 .functor MUXZ 24, L_0x562fb3e846b0, L_0x562fb3e94dd0, L_0x562fb3e84c80, C4<>; -L_0x562fb3e951e0 .functor MUXZ 24, L_0x562fb3e950a0, L_0x562fb3e846b0, L_0x562fb3e830a0, C4<>; -L_0x562fb3e953b0 .part v0x562fb3e822d0_0, 31, 1; -L_0x562fb3e95450 .arith/sum 24, L_0x562fb3e94e70, L_0x7f669afc9180; -L_0x562fb3e956f0 .functor MUXZ 24, L_0x562fb3e84a30, L_0x562fb3e95450, L_0x562fb3e953b0, C4<>; -L_0x562fb3e95830 .functor MUXZ 24, L_0x562fb3e956f0, L_0x562fb3e84a30, L_0x562fb3e830a0, C4<>; -L_0x562fb3e95a70 .concat [ 24 1 0 0], L_0x562fb3e951e0, L_0x7f669afc91c8; -L_0x562fb3e95b60 .concat [ 24 1 0 0], L_0x562fb3e95830, L_0x7f669afc9210; -L_0x562fb3e95e00 .arith/sum 25, L_0x562fb3e95a70, L_0x562fb3e95b60; -L_0x562fb3e95f40 .concat [ 24 1 0 0], L_0x562fb3e846b0, L_0x7f669afc9258; -L_0x562fb3e961a0 .concat [ 24 1 0 0], L_0x562fb3e84a30, L_0x7f669afc92a0; -L_0x562fb3e96290 .arith/sum 25, L_0x562fb3e95f40, L_0x562fb3e954f0; -L_0x562fb3e965c0 .arith/sum 25, L_0x562fb3e96290, L_0x7f669afc92e8; -L_0x562fb3e96700 .functor MUXZ 25, L_0x562fb3e95e00, L_0x562fb3e965c0, v0x562fb3e81df0_0, C4<>; -L_0x562fb3e96a20 .part L_0x562fb3e96700, 24, 1; -L_0x562fb3e96ca0 .arith/sum 25, L_0x562fb3e96c30, L_0x7f669afc9330; -L_0x562fb3e96fa0 .functor MUXZ 25, L_0x562fb3e96ca0, L_0x562fb3e96700, L_0x562fb3e96330, C4<>; -L_0x562fb3e973a0 .part v0x562fb3e82200_0, 31, 1; -L_0x562fb3e975f0 .part v0x562fb3e822d0_0, 31, 1; -L_0x562fb3e97840 .part v0x562fb3e82200_0, 31, 1; -L_0x562fb3e97aa0 .part v0x562fb3e822d0_0, 31, 1; -L_0x562fb3e97db0 .cmp/gt 24, L_0x562fb3e846b0, L_0x562fb3e84a30; -L_0x562fb3e98020 .functor MUXZ 2, L_0x7f669afc9408, L_0x7f669afc93c0, L_0x562fb3e97db0, C4<>; -L_0x562fb3e98160 .part v0x562fb3e82200_0, 31, 1; -L_0x562fb3e983e0 .concat [ 1 1 0 0], L_0x562fb3e98160, L_0x7f669afc9450; -L_0x562fb3e98520 .functor MUXZ 2, L_0x562fb3e983e0, L_0x562fb3e98020, L_0x562fb3e97cb0, C4<>; -L_0x562fb3e988a0 .cmp/gt 24, L_0x562fb3e846b0, L_0x562fb3e84a30; -L_0x562fb3e98940 .part v0x562fb3e82200_0, 31, 1; -L_0x562fb3e98be0 .concat [ 1 1 0 0], L_0x562fb3e98940, L_0x7f669afc9498; -L_0x562fb3e98d20 .part v0x562fb3e822d0_0, 31, 1; -L_0x562fb3e98fd0 .concat [ 1 1 0 0], L_0x562fb3e98d20, L_0x7f669afc94e0; -L_0x562fb3e99110 .functor MUXZ 2, L_0x562fb3e98fd0, L_0x562fb3e98be0, L_0x562fb3e988a0, C4<>; -L_0x562fb3e994c0 .functor MUXZ 2, L_0x562fb3e99110, L_0x562fb3e98520, L_0x562fb3e97780, C4<>; -L_0x562fb3e99650 .part L_0x562fb3e994c0, 0, 1; -L_0x562fb3e99970 .part v0x562fb3e7a780_0, 24, 1; -L_0x562fb3e99a60 .functor MUXZ 8, L_0x562fb3e82d00, L_0x562fb3e82d00, L_0x562fb3e99970, C4<>; -L_0x562fb3e99d90 .functor MUXZ 8, L_0x562fb3e99a60, L_0x562fb3e97260, L_0x562fb3e830a0, C4<>; -L_0x562fb3e99e30 .part L_0x562fb3e96fa0, 24, 1; -L_0x562fb3e9a250 .arith/sum 8, L_0x562fb3e82d00, L_0x7f669afc9528; -L_0x562fb3e9a3b0 .functor MUXZ 8, L_0x562fb3e97260, L_0x562fb3e82d00, L_0x562fb3e830a0, C4<>; -L_0x562fb3e9a740 .functor MUXZ 8, L_0x562fb3e9a3b0, L_0x562fb3e9a250, L_0x562fb3e9a120, C4<>; -L_0x562fb3e9a880 .functor MUXZ 8, L_0x562fb3e9a740, L_0x562fb3e99d90, v0x562fb3e81df0_0, C4<>; -L_0x562fb3e9ac30 .concat8 [ 23 8 1 0], L_0x562fb3e9c9a0, L_0x562fb3e9a880, L_0x562fb3e99650; -L_0x562fb3e9adc0 .part v0x562fb3e7a780_0, 0, 23; -L_0x562fb3e9b0e0 .part v0x562fb3e7a780_0, 24, 1; -L_0x562fb3e9b210 .part v0x562fb3e7a780_0, 1, 23; -L_0x562fb3e9b540 .part v0x562fb3e7a780_0, 0, 23; -L_0x562fb3e9b5e0 .functor MUXZ 23, L_0x562fb3e9b540, L_0x562fb3e9b210, L_0x562fb3e9b0e0, C4<>; -L_0x562fb3e9b9c0 .functor MUXZ 23, L_0x562fb3e9b5e0, L_0x562fb3e9adc0, L_0x562fb3e830a0, C4<>; -L_0x562fb3e9bc10 .part L_0x562fb3e96fa0, 24, 1; -L_0x562fb3e9bf60 .part L_0x562fb3e96fa0, 1, 23; -L_0x562fb3e9c000 .part L_0x562fb3e96fa0, 0, 23; -L_0x562fb3e9c360 .part v0x562fb3e7a780_0, 0, 23; -L_0x562fb3e9c400 .functor MUXZ 23, L_0x562fb3e9c360, L_0x562fb3e9c000, L_0x562fb3e830a0, C4<>; -L_0x562fb3e9c810 .functor MUXZ 23, L_0x562fb3e9c400, L_0x562fb3e9bf60, L_0x562fb3e9a2f0, C4<>; -L_0x562fb3e9c9a0 .functor MUXZ 23, L_0x562fb3e9c810, L_0x562fb3e9b9c0, v0x562fb3e81df0_0, C4<>; -S_0x562fb3df0690 .scope module, "exp_calc0" "exp_calc" 3 42, 4 10 0, S_0x562fb3df2070; - .timescale -6 -9; - .port_info 0 /INPUT 25 "significand"; - .port_info 1 /INPUT 8 "Exponent_a"; - .port_info 2 /OUTPUT 25 "Significand"; - .port_info 3 /OUTPUT 8 "Exponent_sub"; -v0x562fb3def960_0 .net "Exponent_a", 7 0, L_0x562fb3e82d00; alias, 1 drivers -v0x562fb3e7a6a0_0 .net "Exponent_sub", 7 0, L_0x562fb3e97260; alias, 1 drivers -v0x562fb3e7a780_0 .var "Significand", 24 0; -v0x562fb3e7a840_0 .net *"_ivl_0", 7 0, L_0x562fb3e971c0; 1 drivers -L_0x7f669afc9378 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; -v0x562fb3e7a920_0 .net *"_ivl_3", 2 0, L_0x7f669afc9378; 1 drivers -v0x562fb3e7aa50_0 .var "shift", 4 0; -v0x562fb3e7ab30_0 .net "significand", 24 0, L_0x562fb3e96fa0; alias, 1 drivers -E_0x562fb3df79f0 .event edge, v0x562fb3e7ab30_0; -L_0x562fb3e971c0 .concat [ 5 3 0 0], v0x562fb3e7aa50_0, L_0x7f669afc9378; -L_0x562fb3e97260 .arith/sub 8, L_0x562fb3e82d00, L_0x562fb3e971c0; - .scope S_0x562fb3df0690; +S_0x55b7886d6020 .scope module, "fpu" "fpu" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 32 "fpu_in_1"; + .port_info 1 /INPUT 32 "fpu_in_2"; + .port_info 2 /OUTPUT 32 "fpu_output"; +L_0x55b7886f2bf0 .functor BUFZ 32, v0x55b7886f28b0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x55b7886d6250_0 .net *"_ivl_1", 7 0, L_0x55b7886f2a10; 1 drivers +v0x55b7886f1e00_0 .net *"_ivl_3", 7 0, L_0x55b7886f2ab0; 1 drivers +v0x55b7886f1ee0_0 .net *"_ivl_7", 7 0, L_0x55b7886f2cb0; 1 drivers +v0x55b7886f1fa0_0 .net *"_ivl_9", 7 0, L_0x55b7886f2dd0; 1 drivers +v0x55b7886f2080_0 .net "dif_exp", 7 0, L_0x55b7886f2b50; 1 drivers +v0x55b7886f21b0_0 .var "exp", 7 0; +o0x7f3bf390f138 .functor BUFZ 32, C4; HiZ drive +v0x55b7886f2290_0 .net "fpu_in_1", 31 0, o0x7f3bf390f138; 0 drivers +o0x7f3bf390f168 .functor BUFZ 32, C4; HiZ drive +v0x55b7886f2370_0 .net "fpu_in_2", 31 0, o0x7f3bf390f168; 0 drivers +v0x55b7886f2450_0 .net "fpu_output", 31 0, L_0x55b7886f2bf0; 1 drivers +v0x55b7886f2530_0 .var "fpu_reg_1", 22 0; +v0x55b7886f2610_0 .var "fpu_reg_2", 22 0; +v0x55b7886f26f0_0 .var "mantis_sum", 23 0; +v0x55b7886f27d0_0 .net "neg_dif_exp", 7 0, L_0x55b7886f2ec0; 1 drivers +v0x55b7886f28b0_0 .var "tmp_out", 31 0; +E_0x55b7886d91e0/0 .event edge, v0x55b7886f2080_0, v0x55b7886f2290_0, v0x55b7886f2530_0, v0x55b7886f27d0_0; +E_0x55b7886d91e0/1 .event edge, v0x55b7886f2370_0, v0x55b7886f2610_0, v0x55b7886f26f0_0, v0x55b7886f21b0_0; +E_0x55b7886d91e0 .event/or E_0x55b7886d91e0/0, E_0x55b7886d91e0/1; +L_0x55b7886f2a10 .part o0x7f3bf390f138, 23, 8; +L_0x55b7886f2ab0 .part o0x7f3bf390f168, 23, 8; +L_0x55b7886f2b50 .arith/sub 8, L_0x55b7886f2a10, L_0x55b7886f2ab0; +L_0x55b7886f2cb0 .part o0x7f3bf390f168, 23, 8; +L_0x55b7886f2dd0 .part o0x7f3bf390f138, 23, 8; +L_0x55b7886f2ec0 .arith/sub 8, L_0x55b7886f2cb0, L_0x55b7886f2dd0; + .scope S_0x55b7886d6020; T_0 ; - %wait E_0x562fb3df79f0; - %load/vec4 v0x562fb3e7ab30_0; - %dup/vec4; - %pushi/vec4 33554431, 25165823, 25; - %cmp/x; - %jmp/1 T_0.0, 4; - %dup/vec4; - %pushi/vec4 25165823, 20971519, 25; - %cmp/x; - %jmp/1 T_0.1, 4; - %dup/vec4; - %pushi/vec4 20971519, 18874367, 25; - %cmp/x; - %jmp/1 T_0.2, 4; - %dup/vec4; - %pushi/vec4 18874367, 17825791, 25; - %cmp/x; - %jmp/1 T_0.3, 4; - %dup/vec4; - %pushi/vec4 17825791, 17301503, 25; - %cmp/x; - %jmp/1 T_0.4, 4; - %dup/vec4; - %pushi/vec4 17301503, 17039359, 25; - %cmp/x; - %jmp/1 T_0.5, 4; - %dup/vec4; - %pushi/vec4 17039359, 16908287, 25; - %cmp/x; - %jmp/1 T_0.6, 4; - %dup/vec4; - %pushi/vec4 16908287, 16842751, 25; - %cmp/x; - %jmp/1 T_0.7, 4; - %dup/vec4; - %pushi/vec4 16842751, 16809983, 25; - %cmp/x; - %jmp/1 T_0.8, 4; - %dup/vec4; - %pushi/vec4 16809983, 16793599, 25; - %cmp/x; - %jmp/1 T_0.9, 4; - %dup/vec4; - %pushi/vec4 16793599, 16785407, 25; - %cmp/x; - %jmp/1 T_0.10, 4; - %dup/vec4; - %pushi/vec4 16785407, 16781311, 25; - %cmp/x; - %jmp/1 T_0.11, 4; - %dup/vec4; - %pushi/vec4 16781311, 16779263, 25; - %cmp/x; - %jmp/1 T_0.12, 4; - %dup/vec4; - %pushi/vec4 16779263, 16778239, 25; - %cmp/x; - %jmp/1 T_0.13, 4; - %dup/vec4; - %pushi/vec4 16778239, 16777727, 25; - %cmp/x; - %jmp/1 T_0.14, 4; - %dup/vec4; - %pushi/vec4 16777727, 16777471, 25; - %cmp/x; - %jmp/1 T_0.15, 4; - %dup/vec4; - %pushi/vec4 16777471, 16777343, 25; - %cmp/x; - %jmp/1 T_0.16, 4; - %dup/vec4; - %pushi/vec4 16777343, 16777279, 25; - %cmp/x; - %jmp/1 T_0.17, 4; - %dup/vec4; - %pushi/vec4 16777279, 16777247, 25; - %cmp/x; - %jmp/1 T_0.18, 4; - %dup/vec4; - %pushi/vec4 16777247, 16777231, 25; - %cmp/x; - %jmp/1 T_0.19, 4; - %dup/vec4; - %pushi/vec4 16777231, 16777223, 25; - %cmp/x; - %jmp/1 T_0.20, 4; - %dup/vec4; - %pushi/vec4 16777223, 16777219, 25; - %cmp/x; - %jmp/1 T_0.21, 4; - %dup/vec4; - %pushi/vec4 16777219, 16777217, 25; - %cmp/x; - %jmp/1 T_0.22, 4; - %dup/vec4; - %pushi/vec4 16777217, 16777216, 25; - %cmp/x; - %jmp/1 T_0.23, 4; - %dup/vec4; - %pushi/vec4 16777216, 16777216, 25; - %cmp/x; - %jmp/1 T_0.24, 4; - %load/vec4 v0x562fb3e7ab30_0; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 0, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; + %wait E_0x55b7886d91e0; + %load/vec4 v0x55b7886f2080_0; + %parti/s 1, 7, 4; + %cmpi/e 1, 0, 1; + %jmp/0xz T_0.0, 4; + %load/vec4 v0x55b7886f2290_0; + %parti/s 23, 0, 2; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %store/vec4 v0x55b7886f2530_0, 0, 23; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x55b7886f2530_0, 4, 1; + %load/vec4 v0x55b7886f2530_0; + %load/vec4 v0x55b7886f27d0_0; + %pad/u 32; + %subi 1, 0, 32; + %ix/vec4 4; + %shiftr 4; + %store/vec4 v0x55b7886f2530_0, 0, 23; + %load/vec4 v0x55b7886f2370_0; + %parti/s 23, 0, 2; + %store/vec4 v0x55b7886f2610_0, 0, 23; + %load/vec4 v0x55b7886f2370_0; + %parti/s 8, 23, 6; + %store/vec4 v0x55b7886f21b0_0, 0, 8; + %jmp T_0.1; T_0.0 ; - %load/vec4 v0x562fb3e7ab30_0; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 0, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.1 ; - %load/vec4 v0x562fb3e7ab30_0; + %load/vec4 v0x55b7886f2080_0; + %cmpi/u 0, 0, 8; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_0.2, 5; + %load/vec4 v0x55b7886f2370_0; %ix/load 4, 1, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 1, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.2 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 2, 0; + %shiftr 4; + %pad/u 23; + %store/vec4 v0x55b7886f2610_0, 0, 23; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 2, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; + %store/vec4 v0x55b7886f2610_0, 4, 1; + %load/vec4 v0x55b7886f2610_0; + %load/vec4 v0x55b7886f2080_0; + %pad/u 32; + %subi 1, 0, 32; + %ix/vec4 4; + %shiftr 4; + %store/vec4 v0x55b7886f2610_0, 0, 23; + %jmp T_0.3; +T_0.2 ; + %load/vec4 v0x55b7886f2370_0; + %parti/s 23, 0, 2; + %store/vec4 v0x55b7886f2610_0, 0, 23; T_0.3 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 3, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 3, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.4 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 4, 0; + %load/vec4 v0x55b7886f2290_0; + %parti/s 23, 0, 2; + %store/vec4 v0x55b7886f2530_0, 0, 23; + %load/vec4 v0x55b7886f2290_0; + %parti/s 8, 23, 6; + %store/vec4 v0x55b7886f21b0_0, 0, 8; +T_0.1 ; + %load/vec4 v0x55b7886f2530_0; + %pad/u 24; + %load/vec4 v0x55b7886f2610_0; + %pad/u 24; + %add; + %store/vec4 v0x55b7886f26f0_0, 0, 24; + %load/vec4 v0x55b7886f26f0_0; + %parti/s 1, 23, 6; + %cmpi/e 1, 0, 1; + %jmp/0xz T_0.4, 4; + %load/vec4 v0x55b7886f21b0_0; + %addi 1, 0, 8; + %store/vec4 v0x55b7886f21b0_0, 0, 8; + %load/vec4 v0x55b7886f26f0_0; + %ix/load 4, 1, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 4, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.5 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 5, 0; + %shiftr 4; + %store/vec4 v0x55b7886f26f0_0, 0, 24; + %load/vec4 v0x55b7886f2080_0; + %cmpi/e 0, 0, 8; + %jmp/0xz T_0.6, 4; + %pushi/vec4 1, 0, 1; + %ix/load 4, 22, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 5, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; + %store/vec4 v0x55b7886f26f0_0, 4, 1; + %jmp T_0.7; T_0.6 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 6, 0; + %pushi/vec4 0, 0, 1; + %ix/load 4, 22, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 6, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; + %store/vec4 v0x55b7886f26f0_0, 4, 1; T_0.7 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 7, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 7, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.8 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 8, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 8, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.9 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 9, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 9, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.10 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 10, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 10, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.11 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 11, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 11, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.12 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 12, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 12, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.13 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 13, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 13, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.14 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 14, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 14, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.15 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 15, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 15, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.16 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 16, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 16, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.17 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 17, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 17, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.18 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 18, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 18, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.19 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 19, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 19, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.20 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 20, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 20, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.21 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 21, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 21, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.22 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 22, 0; +T_0.4 ; + %pushi/vec4 0, 0, 1; + %ix/load 4, 31, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 22, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.23 ; - %load/vec4 v0x562fb3e7ab30_0; + %store/vec4 v0x55b7886f28b0_0, 4, 1; + %load/vec4 v0x55b7886f21b0_0; %ix/load 4, 23, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 23, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.24 ; - %load/vec4 v0x562fb3e7ab30_0; - %ix/load 4, 24, 0; + %store/vec4 v0x55b7886f28b0_0, 4, 8; + %load/vec4 v0x55b7886f26f0_0; + %parti/s 23, 0, 2; + %ix/load 4, 0, 0; %flag_set/imm 4, 0; - %shiftl 4; - %store/vec4 v0x562fb3e7a780_0, 0, 25; - %pushi/vec4 24, 0, 5; - %store/vec4 v0x562fb3e7aa50_0, 0, 5; - %jmp T_0.26; -T_0.26 ; - %pop/vec4 1; + %store/vec4 v0x55b7886f28b0_0, 4, 23; %jmp T_0; .thread T_0, $push; - .scope S_0x562fb3df3a70; -T_1 ; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x562fb3e81df0_0, 0, 1; - %end; - .thread T_1; - .scope S_0x562fb3df3a70; -T_2 ; - %pushi/vec4 1125960909, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 958817894, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 22 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 22 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 22 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 22 "$display", "\012Sum: %f + %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %pushi/vec4 1142746829, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 3206702694, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 30 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 30 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 30 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 30 "$display", "\012Sum: %f + %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %pushi/vec4 3323776397, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 1059481190, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 38 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 38 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 38 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 38 "$display", "\012Sum: %f + %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %pushi/vec4 3206335693, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 3274072678, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 46 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 46 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 46 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 46 "$display", "\012Sum: %f + %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x562fb3e81df0_0, 0, 1; - %pushi/vec4 1125960909, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 958817894, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 56 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 56 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 56 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 56 "$display", "\012Sum: %f - %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %pushi/vec4 1142746829, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 3206702694, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 64 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 64 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 64 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 64 "$display", "\012Sum: %f - %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %pushi/vec4 3323776397, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 1059481190, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 72 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 72 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 72 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 72 "$display", "\012Sum: %f - %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %pushi/vec4 3206335693, 0, 32; - %store/vec4 v0x562fb3e82200_0, 0, 32; - %pushi/vec4 3274072678, 0, 32; - %store/vec4 v0x562fb3e822d0_0, 0, 32; - %delay 5000, 0; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82200_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81eb0_0, 0, 64; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e822d0_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e81f70_0, 0, 64; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 31, 6; - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 1, 30, 6; - %inv; - %replicate 3; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 7, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x562fb3e82140_0; - %parti/s 23, 0, 2; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 29; - %store/vec4 v0x562fb3e82060_0, 0, 64; - %vpi_func/r 2 80 "$bitstoreal", v0x562fb3e81eb0_0 {0 0 0}; - %vpi_func/r 2 80 "$bitstoreal", v0x562fb3e81f70_0 {0 0 0}; - %vpi_func/r 2 80 "$bitstoreal", v0x562fb3e82060_0 {0 0 0}; - %vpi_call 2 80 "$display", "\012Sum: %f - %f = %f", W<2,r>, W<1,r>, W<0,r> {0 3 0}; - %vpi_call 2 81 "$finish" {0 0 0}; - %end; - .thread T_2; # The file index is used to find the file name in the following table. -:file_names 5; +:file_names 3; "N/A"; ""; - "fpu_bench.v"; - "./fpu_2.v"; - "./exp_calc.v"; + "fpu.v"; diff --git a/verilog/register/a.out b/verilog/register/a.out new file mode 100755 index 0000000..f6d832d --- /dev/null +++ b/verilog/register/a.out @@ -0,0 +1,66 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)" "(v11_0)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/lib/ivl/system.vpi"; +:vpi_module "/usr/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/ivl/va_math.vpi"; +S_0x55bafda5d0c0 .scope module, "registers" "registers" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "writeEnable"; + .port_info 1 /INPUT 1 "clk"; + .port_info 2 /INPUT 32 "addr1"; + .port_info 3 /INPUT 32 "addr2"; + .port_info 4 /INPUT 32 "addr3"; + .port_info 5 /INPUT 32 "writeData"; + .port_info 6 /OUTPUT 32 "readData1"; + .port_info 7 /OUTPUT 32 "readData2"; +L_0x55bafda6fe60 .functor BUFZ 32, L_0x55bafda6fda0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +L_0x55bafda6ffa0 .functor BUFZ 32, L_0x55bafda6fed0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x55bafda5d340_0 .net *"_ivl_0", 31 0, L_0x55bafda6fda0; 1 drivers +v0x55bafda6f380_0 .net *"_ivl_4", 31 0, L_0x55bafda6fed0; 1 drivers +o0x7fee24862078 .functor BUFZ 32, C4; HiZ drive +v0x55bafda6f460_0 .net "addr1", 31 0, o0x7fee24862078; 0 drivers +o0x7fee248620a8 .functor BUFZ 32, C4; HiZ drive +v0x55bafda6f520_0 .net "addr2", 31 0, o0x7fee248620a8; 0 drivers +o0x7fee248620d8 .functor BUFZ 32, C4; HiZ drive +v0x55bafda6f600_0 .net "addr3", 31 0, o0x7fee248620d8; 0 drivers +o0x7fee24862108 .functor BUFZ 1, C4; HiZ drive +v0x55bafda6f730_0 .net "clk", 0 0, o0x7fee24862108; 0 drivers +v0x55bafda6f7f0_0 .net "readData1", 31 0, L_0x55bafda6fe60; 1 drivers +v0x55bafda6f8d0_0 .net "readData2", 31 0, L_0x55bafda6ffa0; 1 drivers +v0x55bafda6f9b0 .array "register", 31 0, 31 0; +o0x7fee24862198 .functor BUFZ 32, C4; HiZ drive +v0x55bafda6fb00_0 .net "writeData", 31 0, o0x7fee24862198; 0 drivers +o0x7fee248621c8 .functor BUFZ 1, C4; HiZ drive +v0x55bafda6fbe0_0 .net "writeEnable", 0 0, o0x7fee248621c8; 0 drivers +E_0x55bafda5d640 .event posedge, v0x55bafda6f730_0; +L_0x55bafda6fda0 .array/port v0x55bafda6f9b0, o0x7fee24862078; +L_0x55bafda6fed0 .array/port v0x55bafda6f9b0, o0x7fee248620a8; + .scope S_0x55bafda5d0c0; +T_0 ; + %wait E_0x55bafda5d640; + %load/vec4 v0x55bafda6fbe0_0; + %flag_set/vec4 8; + %jmp/0 T_0.0, 8; + %load/vec4 v0x55bafda6fb00_0; + %jmp/1 T_0.1, 8; +T_0.0 ; End of true expr. + %ix/getv 4, v0x55bafda6f600_0; + %load/vec4a v0x55bafda6f9b0, 4; + %jmp/0 T_0.1, 8; + ; End of false expr. + %blend; +T_0.1; + %ix/getv 3, v0x55bafda6f600_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55bafda6f9b0, 0, 4; + %jmp T_0; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "registers.v"; diff --git a/verilog/register/registers.v b/verilog/register/registers.v new file mode 100644 index 0000000..f2dbb22 --- /dev/null +++ b/verilog/register/registers.v @@ -0,0 +1,22 @@ +module registers( + input wire writeEnable, + input wire clk, + input wire [31:0] addr1, + input wire [31:0] addr2, + input wire [31:0] addr3, + input wire [31:0] writeData, + output wire [31:0] readData1, + output wire [31:0] readData2 +); + +reg [31:0] register [0:31]; + +always @ (posedge clk) +begin + register[addr3] <= writeEnable ? writeData : register[addr3]; +end + +assign readData1 = register[addr1]; +assign readData2 = register[addr2]; + +endmodule diff --git a/verilog/riscv_alu.v b/verilog/riscv_alu.v deleted file mode 100644 index 87dd637..0000000 --- a/verilog/riscv_alu.v +++ /dev/null @@ -1,39 +0,0 @@ -module riscv_alu -( -input wire signed [31:0] alu_in_1, -input wire[31:0] alu_in_2, -input wire[3:0] alu_op_i, -output wire[31:0] alu_output -); - -reg[31:0] tmp_out; -`include "alu_ops.vh" - -wire [31:0] sub_alu = alu_in_1 - alu_in_2; - -always @(*) -begin - case (alu_op_i) - `ADD: tmp_out = alu_in_1 + alu_in_2; - `SUB: tmp_out = sub_alu; - `XOR: tmp_out = alu_in_1 ^ alu_in_2; - `OR: tmp_out = alu_in_1 | alu_in_2; - `AND: tmp_out = alu_in_1 & alu_in_2; - `SLL: tmp_out = alu_in_1 << alu_in_2; - `SRL: tmp_out = alu_in_1 >> alu_in_2; - `SRA: tmp_out = alu_in_1 >>> alu_in_2; - `SLT: tmp_out = (alu_in_1 < alu_in_2) ? 32'h1 : 32'h0; - `SLTU: - begin - if (alu_in_1[31] != alu_in_2[31]) - tmp_out = alu_in_1[31] ? 32'h1 : 32'h0; - else - tmp_out = sub_alu[31] ? 32'h1 : 32'h0; - end - default: tmp_out = alu_in_1; - endcase -end - -assign alu_output = tmp_out; - -endmodule -- cgit v1.2.3