From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001
From: Joshua Yun <jjyun4@illinois.edu>
Date: Mon, 28 Aug 2023 14:42:23 -0500
Subject: Added new riscv processor design into git repo

---
 verilog/Makefile | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 verilog/Makefile

(limited to 'verilog/Makefile')

diff --git a/verilog/Makefile b/verilog/Makefile
new file mode 100644
index 0000000..4775c0d
--- /dev/null
+++ b/verilog/Makefile
@@ -0,0 +1,10 @@
+datapath_test:
+	verilator --trace --cc --exe --build -j 0 -Wall tbdatapath.cpp datapath.v
+	./obj_dir/Vdatapath
+datapath_synth:
+	yosys -p "read_verilog datapath.v ; hierarchy -top datapath -libdir . ; synth_ecp5"
+clean:
+	rm -rf log_* obj_dir
+alu_test:
+	verilator --cc --exe --build -j 0 -Wall tbalu.cpp alu.v
+	./obj_dir/Valu
-- 
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