From 9dc6d7180438031d25daf6a68a3959c3cfa9312d Mon Sep 17 00:00:00 2001 From: joshua Date: Tue, 14 Dec 2021 01:46:40 -0600 Subject: Initial Commit --- verilog/a.out | 202 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100755 verilog/a.out (limited to 'verilog/a.out') diff --git a/verilog/a.out b/verilog/a.out new file mode 100755 index 0000000..77036bc --- /dev/null +++ b/verilog/a.out @@ -0,0 +1,202 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)" "(v11_0)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 9; +:vpi_module "/usr/lib/ivl/system.vpi"; +:vpi_module "/usr/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/ivl/va_math.vpi"; +S_0x5585f3becd70 .scope module, "bench_alu" "bench_alu" 2 6; + .timescale -6 -9; +v0x5585f3c3e500_0 .net "alu_out", 31 0, L_0x5585f3c3e890; 1 drivers +v0x5585f3c3e5e0_0 .var "input1", 31 0; +v0x5585f3c3e680_0 .var "input2", 31 0; +v0x5585f3c3e720_0 .var "op", 3 0; +S_0x5585f3becf00 .scope module, "alu0" "riscv_alu" 2 12, 3 1 0, S_0x5585f3becd70; + .timescale -6 -9; + .port_info 0 /INPUT 32 "alu_in_1"; + .port_info 1 /INPUT 32 "alu_in_2"; + .port_info 2 /INPUT 4 "alu_op_i"; + .port_info 3 /OUTPUT 32 "alu_output"; +L_0x5585f3c3e890 .functor BUFZ 32, v0x5585f3c3e3a0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0x5585f3c29b30_0 .net/s "alu_in_1", 31 0, v0x5585f3c3e5e0_0; 1 drivers +v0x5585f3c3dff0_0 .net "alu_in_2", 31 0, v0x5585f3c3e680_0; 1 drivers +v0x5585f3c3e0d0_0 .net "alu_op_i", 3 0, v0x5585f3c3e720_0; 1 drivers +v0x5585f3c3e190_0 .net "alu_output", 31 0, L_0x5585f3c3e890; alias, 1 drivers +v0x5585f3c3e270_0 .net "sub_alu", 31 0, L_0x5585f3c3e7f0; 1 drivers +v0x5585f3c3e3a0_0 .var "tmp_out", 31 0; +E_0x5585f3c2a2f0 .event edge, v0x5585f3c3e0d0_0, v0x5585f3c29b30_0, v0x5585f3c3dff0_0, v0x5585f3c3e270_0; +L_0x5585f3c3e7f0 .arith/sub 32, v0x5585f3c3e5e0_0, v0x5585f3c3e680_0; + .scope S_0x5585f3becf00; +T_0 ; + %wait E_0x5585f3c2a2f0; + %load/vec4 v0x5585f3c3e0d0_0; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_0.7, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_0.8, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_0.9, 6; + %load/vec4 v0x5585f3c29b30_0; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.0 ; + %load/vec4 v0x5585f3c29b30_0; + %load/vec4 v0x5585f3c3dff0_0; + %add; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.1 ; + %load/vec4 v0x5585f3c3e270_0; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.2 ; + %load/vec4 v0x5585f3c29b30_0; + %load/vec4 v0x5585f3c3dff0_0; + %xor; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.3 ; + %load/vec4 v0x5585f3c29b30_0; + %load/vec4 v0x5585f3c3dff0_0; + %or; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.4 ; + %load/vec4 v0x5585f3c29b30_0; + %load/vec4 v0x5585f3c3dff0_0; + %and; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.5 ; + %load/vec4 v0x5585f3c29b30_0; + %ix/getv 4, v0x5585f3c3dff0_0; + %shiftl 4; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.6 ; + %load/vec4 v0x5585f3c29b30_0; + %ix/getv 4, v0x5585f3c3dff0_0; + %shiftr 4; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.7 ; + %load/vec4 v0x5585f3c29b30_0; + %ix/getv 4, v0x5585f3c3dff0_0; + %shiftr/s 4; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.8 ; + %load/vec4 v0x5585f3c29b30_0; + %load/vec4 v0x5585f3c3dff0_0; + %cmp/u; + %flag_mov 8, 5; + %jmp/0 T_0.12, 8; + %pushi/vec4 1, 0, 32; + %jmp/1 T_0.13, 8; +T_0.12 ; End of true expr. + %pushi/vec4 0, 0, 32; + %jmp/0 T_0.13, 8; + ; End of false expr. + %blend; +T_0.13; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.11; +T_0.9 ; + %load/vec4 v0x5585f3c29b30_0; + %parti/s 1, 31, 6; + %load/vec4 v0x5585f3c3dff0_0; + %parti/s 1, 31, 6; + %cmp/ne; + %jmp/0xz T_0.14, 4; + %load/vec4 v0x5585f3c29b30_0; + %parti/s 1, 31, 6; + %flag_set/vec4 8; + %jmp/0 T_0.16, 8; + %pushi/vec4 1, 0, 32; + %jmp/1 T_0.17, 8; +T_0.16 ; End of true expr. + %pushi/vec4 0, 0, 32; + %jmp/0 T_0.17, 8; + ; End of false expr. + %blend; +T_0.17; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; + %jmp T_0.15; +T_0.14 ; + %load/vec4 v0x5585f3c3e270_0; + %parti/s 1, 31, 6; + %flag_set/vec4 8; + %jmp/0 T_0.18, 8; + %pushi/vec4 1, 0, 32; + %jmp/1 T_0.19, 8; +T_0.18 ; End of true expr. + %pushi/vec4 0, 0, 32; + %jmp/0 T_0.19, 8; + ; End of false expr. + %blend; +T_0.19; + %store/vec4 v0x5585f3c3e3a0_0, 0, 32; +T_0.15 ; + %jmp T_0.11; +T_0.11 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x5585f3becd70; +T_1 ; + %pushi/vec4 11, 0, 4; + %store/vec4 v0x5585f3c3e720_0, 0, 4; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x5585f3c3e5e0_0, 0, 32; + %pushi/vec4 13, 0, 32; + %store/vec4 v0x5585f3c3e680_0, 0, 32; + %delay 50000, 0; + %load/vec4 v0x5585f3c3e5e0_0; + %load/vec4 v0x5585f3c3e680_0; + %load/vec4 v0x5585f3c3e500_0; + %vpi_call 2 19 "$display", "\012ALU OP AND: %d %16b + %d %16b = %d %b", S<2,vec4,s32>, v0x5585f3c3e5e0_0, S<1,vec4,s32>, v0x5585f3c3e680_0, S<0,vec4,s32>, v0x5585f3c3e500_0 {3 0 0}; + %vpi_call 2 20 "$finish" {0 0 0}; + %end; + .thread T_1; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "bench_alu.v"; + "./riscv_alu.v"; -- cgit v1.2.3