From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 14 May 2022 23:30:38 -0500 Subject: Verilog update --- verilog/alu/obj_dir/Valu__Syms.cpp | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 verilog/alu/obj_dir/Valu__Syms.cpp (limited to 'verilog/alu/obj_dir/Valu__Syms.cpp') diff --git a/verilog/alu/obj_dir/Valu__Syms.cpp b/verilog/alu/obj_dir/Valu__Syms.cpp new file mode 100644 index 0000000..bd9fdd1 --- /dev/null +++ b/verilog/alu/obj_dir/Valu__Syms.cpp @@ -0,0 +1,26 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Valu__Syms.h" +#include "Valu.h" +#include "Valu___024root.h" + +// FUNCTIONS +Valu__Syms::~Valu__Syms() +{ +} + +Valu__Syms::Valu__Syms(VerilatedContext* contextp, const char* namep,Valu* modelp) + : VerilatedSyms{contextp} + // Setup internal state of the Syms class + , __Vm_modelp{modelp} + // Setup module instances + , TOP(namep) +{ + // Configure time unit / time precision + _vm_contextp__->timeunit(-6); + _vm_contextp__->timeprecision(-9); + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOP.__Vconfigure(this, true); +} -- cgit v1.2.3