From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 14 May 2022 23:30:38 -0500 Subject: Verilog update --- verilog/alu/obj_dir/Valu___024root.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 verilog/alu/obj_dir/Valu___024root.h (limited to 'verilog/alu/obj_dir/Valu___024root.h') diff --git a/verilog/alu/obj_dir/Valu___024root.h b/verilog/alu/obj_dir/Valu___024root.h new file mode 100644 index 0000000..18b3f2f --- /dev/null +++ b/verilog/alu/obj_dir/Valu___024root.h @@ -0,0 +1,34 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Valu.h for the primary calling header + +#ifndef VERILATED_VALU___024ROOT_H_ +#define VERILATED_VALU___024ROOT_H_ // guard + +#include "verilated.h" + +class Valu__Syms; +VL_MODULE(Valu___024root) { + public: + + // DESIGN SPECIFIC STATE + VL_IN8(op,3,0); + VL_IN(in1,31,0); + VL_IN(in2,31,0); + VL_OUT(out,31,0); + IData/*31:0*/ alu__DOT__result; + + // INTERNAL VARIABLES + Valu__Syms* vlSymsp; // Symbol table + + // CONSTRUCTORS + Valu___024root(const char* name); + ~Valu___024root(); + VL_UNCOPYABLE(Valu___024root); + + // INTERNAL METHODS + void __Vconfigure(Valu__Syms* symsp, bool first); +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + + +#endif // guard -- cgit v1.2.3