From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/alu/v1/alu.v | 34 ---------------------------------- 1 file changed, 34 deletions(-) delete mode 100644 verilog/alu/v1/alu.v (limited to 'verilog/alu/v1/alu.v') diff --git a/verilog/alu/v1/alu.v b/verilog/alu/v1/alu.v deleted file mode 100644 index cb66ddb..0000000 --- a/verilog/alu/v1/alu.v +++ /dev/null @@ -1,34 +0,0 @@ -`default_nettype none -`timescale 1us/1ns - -`include "aluOp.vh" - -module alu -( -input wire [31:0] alu_in_1, -input wire[31:0] alu_in_2, -input wire[3:0] alu_op_i, -output wire[31:0] alu_output -); - - -wire [31:0] diff = alu_in_1 - alu_in_2; - -assign alu_output = - alu_op_i == `ADD ? alu_in_1 + alu_in_2 : - alu_op_i == `SUB ? diff : - alu_op_i == `XOR ? alu_in_1 ^ alu_in_2 : - alu_op_i == `OR ? alu_in_1 | alu_in_2 : - alu_op_i == `AND ? alu_in_1 & alu_in_2 : - alu_op_i == `SLL ? alu_in_1 << alu_in_2 : - alu_op_i == `SRL ? alu_in_1 >> alu_in_2 : - alu_op_i == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : - alu_op_i == `NONE ? alu_in_1 : - alu_op_i == `SLT ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 1'b0 ? 32'b0 : 32'b1) : (alu_in_1[31] == 1'b1 ? 32'b1 : 32'b0) ) : - alu_op_i == `SRA ? (alu_in_1 >> alu_in_2) | (alu_in_1[31] == 1'b0 ? 32'b0 : - 32'hFFFFFFFF << ((alu_in_2[4] ? 0 : 5'b10000) + (alu_in_2[3] ? 0 : 5'b01000) + - (alu_in_2[2] ? 0 : 5'b00100) + (alu_in_2[1] ? 0 : 5'b00010) + (alu_in_2[0] ? 0 : 5'b00001)) - ) : - 32'b0; - -endmodule -- cgit v1.2.3