From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/alu/v2/Makefile | 35 ------- verilog/alu/v2/alu2.v | 40 -------- verilog/alu/v2/aluOp.h | 16 --- verilog/alu/v2/aluOp.vh | 16 --- verilog/alu/v2/crab.pcf | 254 ----------------------------------------------- verilog/alu/v2/tbalu.cpp | 45 --------- 6 files changed, 406 deletions(-) delete mode 100644 verilog/alu/v2/Makefile delete mode 100644 verilog/alu/v2/alu2.v delete mode 100644 verilog/alu/v2/aluOp.h delete mode 100644 verilog/alu/v2/aluOp.vh delete mode 100644 verilog/alu/v2/crab.pcf delete mode 100644 verilog/alu/v2/tbalu.cpp (limited to 'verilog/alu/v2') diff --git a/verilog/alu/v2/Makefile b/verilog/alu/v2/Makefile deleted file mode 100644 index 6de97ff..0000000 --- a/verilog/alu/v2/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -PROJ=alu2 -VERION:=r0.2 -RM = rm -rf -COPY = cp -a -PATH_SEP = / - - -crab: ${PROJ}.dfu - -dfu: ${PROJ}.dfu - dfu-util -D $< - - -%.json: %.v - yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" - -%_out.config: %.json - nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf - -%.bit: %_out.config - ecppack --compress --freq 38.8 --input $< --bit $@ - -%.dfu : %.bit - $(COPY) $< $@ - dfu-suffix -v 1209 -p 5af0 -a $@ - -sim: - verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out -simclean: - rm -rf obj_dir/* out - -clean: - $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu - -.PHONY: prog clean diff --git a/verilog/alu/v2/alu2.v b/verilog/alu/v2/alu2.v deleted file mode 100644 index d7a0324..0000000 --- a/verilog/alu/v2/alu2.v +++ /dev/null @@ -1,40 +0,0 @@ -`default_nettype none -`timescale 1us/1ns - -`include "aluOp.vh" - -module alu2 -( -input wire [31:0] in1, -input wire[31:0] in2, -input wire[3:0] op, -output wire[31:0] out -); - - -wire [31:0] diff = in1 - in2; -reg [31:0] result; - -always @ (*) -begin - case (op) - `ADD: result = in1 + in2; - `SUB: result = diff; - `XOR: result = in1 ^ in2; - `OR: result = in1 | in2; - `AND: result = in1 & in2; - `SLL: result = in1 << in2; - `SRL: result = in1 >> in2; - `SLTU: result = (in1 < in2 ? 32'b1 : 32'b0); - `NONE: result = in1; - `SLT: result = (in1[31] == in2[31] ? (diff[31] == 1'b0 ? 32'b0 : 32'b1) : (in1[31] == 1'b1 ? 32'b1 : 32'b0) ); - `SRA: result = (in1 >> in2) | (in1[31] == 1'b0 ? 32'b0 : - 32'hFFFFFFFF << ((in2[4] ? 0 : 5'b10000) + (in2[3] ? 0 : 5'b01000) + - (in2[2] ? 0 : 5'b00100) + (in2[1] ? 0 : 5'b00010) + (in2[0] ? 0 : 5'b00001)) - ); - default: result = 32'b0; - endcase -end - -assign out = result; -endmodule diff --git a/verilog/alu/v2/aluOp.h b/verilog/alu/v2/aluOp.h deleted file mode 100644 index 999dac2..0000000 --- a/verilog/alu/v2/aluOp.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef ALU_OP -#define ALU_OP - -#define ADD 0 -#define SUB 8 -#define XOR 4 -#define OR 6 -#define AND 7 -#define SLL 1 -#define SRL 5 -#define SRA 13 -#define SLT 2 -#define SLTU 3 -#define NONE 15 - -#endif diff --git a/verilog/alu/v2/aluOp.vh b/verilog/alu/v2/aluOp.vh deleted file mode 100644 index b6e916f..0000000 --- a/verilog/alu/v2/aluOp.vh +++ /dev/null @@ -1,16 +0,0 @@ -`ifndef ALU_OP -`define ALU_OP - -`define ADD 4'b0000 -`define SUB 4'b1000 -`define XOR 4'b0100 -`define OR 4'b0110 -`define AND 4'b0111 -`define SLL 4'b0001 -`define SRL 4'b0101 -`define SRA 4'b1101 -`define SLT 4'b0010 -`define SLTU 4'b0011 -`define NONE 4'b1111 - -`endif diff --git a/verilog/alu/v2/crab.pcf b/verilog/alu/v2/crab.pcf deleted file mode 100644 index c0d91c5..0000000 --- a/verilog/alu/v2/crab.pcf +++ /dev/null @@ -1,254 +0,0 @@ -LOCATE COMP "clk48" SITE "A9"; -IOBUF PORT "clk48" IO_TYPE=LVCMOS33; -FREQUENCY PORT "clk48" 48.0 MHz; - -LOCATE COMP "ddram_a[0]" SITE "C4"; -IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[1]" SITE "D2"; -IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[2]" SITE "D3"; -IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[3]" SITE "A3"; -IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[4]" SITE "A4"; -IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[5]" SITE "D4"; -IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[6]" SITE "C3"; -IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[7]" SITE "B2"; -IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[8]" SITE "B1"; -IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[9]" SITE "D1"; -IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[10]" SITE "A7"; -IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[11]" SITE "C2"; -IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[12]" SITE "B6"; -IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[13]" SITE "C1"; -IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[14]" SITE "A2"; -IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_a[15]" SITE "C7"; -IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; -IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_ba[0]" SITE "D6"; -IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; -IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_ba[1]" SITE "B7"; -IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; -IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_ba[2]" SITE "A6"; -IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; -IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_ras_n" SITE "C12"; -IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; -IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_cas_n" SITE "D13"; -IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; -IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_we_n" SITE "B12"; -IOBUF PORT "ddram_we_n" SLEWRATE=FAST; -IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_cs_n" SITE "A12"; -IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; -IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_dm[0]" SITE "D16"; -IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; -IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_dm[1]" SITE "G16"; -IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; -IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_dq[0]" SITE "C17"; -IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[1]" SITE "D15"; -IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[2]" SITE "B17"; -IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[3]" SITE "C16"; -IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[4]" SITE "A15"; -IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[5]" SITE "B13"; -IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[6]" SITE "A17"; -IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[7]" SITE "A13"; -IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[8]" SITE "F17"; -IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[9]" SITE "F16"; -IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[10]" SITE "G15"; -IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[11]" SITE "F15"; -IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[12]" SITE "J16"; -IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[13]" SITE "C18"; -IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[14]" SITE "H16"; -IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; -LOCATE COMP "ddram_dq[15]" SITE "F18"; -IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; -IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; -IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; -LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; -IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; -IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; -IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; -IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; -LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; -IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; -IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; -IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; -IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; -LOCATE COMP "ddram_clk_p" SITE "J18"; -IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; -IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; -LOCATE COMP "ddram_cke" SITE "D18"; -IOBUF PORT "ddram_cke" SLEWRATE=FAST; -IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_odt" SITE "C13"; -IOBUF PORT "ddram_odt" SLEWRATE=FAST; -IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_reset_n" SITE "L18"; -IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; -IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; -LOCATE COMP "ddram_vccio[0]" SITE "K16"; -IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; -IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; -LOCATE COMP "ddram_vccio[1]" SITE "D17"; -IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; -IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; -LOCATE COMP "ddram_vccio[2]" SITE "K15"; -IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; -IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; -LOCATE COMP "ddram_vccio[3]" SITE "K17"; -IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; -IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; -LOCATE COMP "ddram_vccio[4]" SITE "B18"; -IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; -IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; -LOCATE COMP "ddram_vccio[5]" SITE "C6"; -IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; -IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; -LOCATE COMP "ddram_gnd[0]" SITE "L15"; -IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; -IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; -LOCATE COMP "ddram_gnd[1]" SITE "L16"; -IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; -IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; -LOCATE COMP "rgb_led0_r" SITE "K4"; -IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; -LOCATE COMP "rgb_led0_g" SITE "M3"; -IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; -LOCATE COMP "rgb_led0_b" SITE "J3"; -IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; -LOCATE COMP "gpio_0" SITE "N17"; -IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_0" PULLMODE=DOWN; -LOCATE COMP "gpio_1" SITE "M18"; -IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_1" PULLMODE=DOWN; -LOCATE COMP "gpio_5" SITE "B10"; -IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_5" PULLMODE=DOWN; -LOCATE COMP "gpio_6" SITE "B9"; -IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_6" PULLMODE=DOWN; -LOCATE COMP "gpio_9" SITE "C8"; -IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_9" PULLMODE=DOWN; -LOCATE COMP "gpio_10" SITE "B8"; -IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_10" PULLMODE=DOWN; -LOCATE COMP "gpio_11" SITE "A8"; -IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_11" PULLMODE=DOWN; -LOCATE COMP "gpio_12" SITE "H2"; -IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_12" PULLMODE=DOWN; -LOCATE COMP "gpio_13" SITE "J2"; -IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_13" PULLMODE=DOWN; -LOCATE COMP "gpio_a0" SITE "L4"; -IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_a0" PULLMODE=DOWN; -LOCATE COMP "gpio_a1" SITE "N3"; -IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_a1" PULLMODE=DOWN; -LOCATE COMP "gpio_a2" SITE "N4"; -IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_a2" PULLMODE=DOWN; -LOCATE COMP "gpio_a3" SITE "H4"; -IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio_a3" PULLMODE=DOWN; -LOCATE COMP "usr_btn" SITE "J17"; -IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; -LOCATE COMP "rst_n" SITE "V17"; -IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; -LOCATE COMP "spiflash4x_cs_n" SITE "U17"; -IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; -LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; -IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; -IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; -IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; -IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; -LOCATE COMP "usb_d_p" SITE "N1"; -IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; -LOCATE COMP "usb_d_n" SITE "M2"; -IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; -LOCATE COMP "usb_pullup" SITE "N2"; -IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; diff --git a/verilog/alu/v2/tbalu.cpp b/verilog/alu/v2/tbalu.cpp deleted file mode 100644 index b3947f8..0000000 --- a/verilog/alu/v2/tbalu.cpp +++ /dev/null @@ -1,45 +0,0 @@ -#include -#include -#include -#include -#include "Valu.h" -#include "aluOp.h" -#define OP SRA -#define OPSTR "SRA" -#define SIGN "SRA" -#define LOWER -10 -#define UPPER 0 - -vluint64_t sim_time = 0; - -int main(int argc, char** argv, char** env) { - Valu *dut = new Valu; - - Verilated::traceEverOn(true); - VerilatedVcdC *m_trace = new VerilatedVcdC; - dut->trace(m_trace, 5); - m_trace->open("waveform.vcd"); - - dut->op = OP; - for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) { - for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { - dut->eval(); - std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n"; - sim_time++; - m_trace->dump(sim_time); - } - } - - for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) { - for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { - dut->eval(); - std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n"; - sim_time++; - m_trace->dump(sim_time); - } - } - - m_trace->close(); - delete dut; - exit(EXIT_SUCCESS); -} -- cgit v1.2.3