From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001
From: Joshua Yun <jjyun4@illinois.edu>
Date: Mon, 28 Aug 2023 14:42:23 -0500
Subject: Added new riscv processor design into git repo

---
 verilog/alu/v3/aluOp.vh | 16 ----------------
 1 file changed, 16 deletions(-)
 delete mode 100644 verilog/alu/v3/aluOp.vh

(limited to 'verilog/alu/v3/aluOp.vh')

diff --git a/verilog/alu/v3/aluOp.vh b/verilog/alu/v3/aluOp.vh
deleted file mode 100644
index b6e916f..0000000
--- a/verilog/alu/v3/aluOp.vh
+++ /dev/null
@@ -1,16 +0,0 @@
-`ifndef ALU_OP
-`define ALU_OP
-
-`define ADD             4'b0000
-`define SUB             4'b1000
-`define XOR             4'b0100
-`define OR              4'b0110
-`define AND             4'b0111
-`define SLL             4'b0001
-`define SRL             4'b0101
-`define SRA             4'b1101
-`define SLT             4'b0010
-`define SLTU            4'b0011
-`define NONE            4'b1111
-
-`endif
-- 
cgit v1.2.3