From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 14 May 2022 23:30:38 -0500 Subject: Verilog update --- verilog/alu/v5/alu5.v | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 verilog/alu/v5/alu5.v (limited to 'verilog/alu/v5/alu5.v') diff --git a/verilog/alu/v5/alu5.v b/verilog/alu/v5/alu5.v new file mode 100644 index 0000000..4670c19 --- /dev/null +++ b/verilog/alu/v5/alu5.v @@ -0,0 +1,30 @@ +`default_nettype none +`timescale 1us/1ns + +`include "aluOp.vh" + +module alu5 +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + + +wire [31:0] diff = alu_in_1 - alu_in_2; + +assign alu_output = + alu_op_i == `NONE ? alu_in_1 : + alu_op_i == `ADD ? alu_in_1 + alu_in_2 : + alu_op_i == `SUB ? diff : + alu_op_i == `XOR ? alu_in_1 ^ alu_in_2 : + alu_op_i == `OR ? alu_in_1 | alu_in_2 : + alu_op_i == `AND ? alu_in_1 & alu_in_2 : + alu_op_i == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : + alu_op_i == `SLT ? (alu_in_1[31] == alu_in_2[31] ? {31'b0, diff[31]} : {31'b0, alu_in_1[31]}) : + alu_op_i == `SLL ? alu_in_1 << alu_in_2 : + alu_op_i == `SRL ? alu_in_1 >> alu_in_2 : + alu_op_i == `SRA ? (alu_in_1 >> alu_in_2) | (alu_in_1[31] == 1'b0 ? 32'b0 : (32'hFFFFFFFF << {~alu_in_2[4], ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]})) : + 32'b0; +endmodule -- cgit v1.2.3