From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/alu/v6/LUTS | 172 ---------------------------------------------------- 1 file changed, 172 deletions(-) delete mode 100644 verilog/alu/v6/LUTS (limited to 'verilog/alu/v6/LUTS') diff --git a/verilog/alu/v6/LUTS b/verilog/alu/v6/LUTS deleted file mode 100644 index ec716bd..0000000 --- a/verilog/alu/v6/LUTS +++ /dev/null @@ -1,172 +0,0 @@ - -ADD SUB no share - - Number of wires: 233 - Number of wire bits: 644 - Number of public wires: 233 - Number of public wire bits: 644 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 256 - CCU2C 32 - L6MUX21 32 - LUT4 128 - PFUMX 64 - - - -ADD SUB Sharing - - Number of wires: 12 - Number of wire bits: 356 - Number of public wires: 12 - Number of public wire bits: 356 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 128 - CCU2C 32 - LUT4 96 - -XOR - - Number of wires: 204 - Number of wire bits: 548 - Number of public wires: 204 - Number of public wire bits: 548 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 320 - CCU2C 32 - L6MUX21 32 - LUT4 192 - PFUMX 64 - - -AND + OR - - Number of wires: 204 - Number of wire bits: 548 - Number of public wires: 204 - Number of public wire bits: 548 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 320 - CCU2C 32 - L6MUX21 32 - LUT4 192 - PFUMX 64 - - - Number of wires: 212 - Number of wire bits: 556 - Number of public wires: 212 - Number of public wire bits: 556 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 328 - CCU2C 32 - L6MUX21 34 - LUT4 196 - PFUMX 66 - - -=== alu6 === - - Number of wires: 529 - Number of wire bits: 1122 - Number of public wires: 529 - Number of public wire bits: 1122 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 731 - CCU2C 32 - L6MUX21 66 - LUT4 475 - PFUMX 158 - -=== alu6 === Shift left - - Number of wires: 526 - Number of wire bits: 1100 - Number of public wires: 526 - Number of public wire bits: 1100 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 730 - CCU2C 32 - L6MUX21 67 - LUT4 473 - PFUMX 158 - -Shift right - - Number of wires: 1161 - Number of wire bits: 2070 - Number of public wires: 1161 - Number of public wire bits: 2070 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 1456 - CCU2C 32 - L6MUX21 174 - LUT4 923 - PFUMX 327 - -Shift right muxed - -=== alu6 === - - Number of wires: 843 - Number of wire bits: 1731 - Number of public wires: 843 - Number of public wire bits: 1731 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 1134 - CCU2C 32 - L6MUX21 103 - LUT4 756 - PFUMX 243 - -Set less than signed - -=== alu6 === - - Number of wires: 843 - Number of wire bits: 1731 - Number of public wires: 843 - Number of public wire bits: 1731 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 1134 - CCU2C 32 - L6MUX21 103 - LUT4 756 - PFUMX 243 - -Set less than unsigned - -=== alu6 === - - Number of wires: 871 - Number of wire bits: 1857 - Number of public wires: 871 - Number of public wire bits: 1857 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 1183 - CCU2C 48 - L6MUX21 109 - LUT4 778 - PFUMX 248 -- cgit v1.2.3