From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001
From: Joshua Yun <jjyun4@illinois.edu>
Date: Mon, 28 Aug 2023 14:42:23 -0500
Subject: Added new riscv processor design into git repo

---
 verilog/alu/v6/Makefile | 40 ----------------------------------------
 1 file changed, 40 deletions(-)
 delete mode 100644 verilog/alu/v6/Makefile

(limited to 'verilog/alu/v6/Makefile')

diff --git a/verilog/alu/v6/Makefile b/verilog/alu/v6/Makefile
deleted file mode 100644
index 02598ac..0000000
--- a/verilog/alu/v6/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-PROJ=alu6
-VERION:=r0.2
-RM = rm -rf
-COPY = cp -a
-PATH_SEP = /
-
-
-crab: ${PROJ}.dfu
-
-dfu: ${PROJ}.dfu
-	dfu-util -D $<
-
-
-%.json: %.v
-	yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@"
-
-%_out.config: %.json
-	nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf
-
-%.bit: %_out.config
-	ecppack --compress --freq 38.8 --input $< --bit $@
-
-%.dfu : %.bit
-	$(COPY) $< $@
-	dfu-suffix -v 1209 -p 5af0 -a $@
-
-sim:
-	verilator -Wall --cc --exe --build tbalu.cpp alu6.v --trace && ./obj_dir/Valu6 > out
-simgate:
-	yosys -p "read_verilog ${PROJ}.v; synth_ecp5 -top ${PROJ} -blif ${PROJ}.blif"
-	yosys -o synth_${PROJ}.v ${PROJ}.blif
-	verilator -Wall --cc --exe --build tbalu.cpp synth_alu6.v --trace && ./obj_dir/Valu6 > out
-
-simclean:
-	rm -rf obj_dir/* out waveform.vcd
-
-clean:
-	$(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu
-
-.PHONY: prog clean
-- 
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