From d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 Mon Sep 17 00:00:00 2001
From: joshua <joshua@joshuayun.com>
Date: Mon, 16 May 2022 11:05:49 -0400
Subject: Fixed gitignore

---
 verilog/alu/v6/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'verilog/alu/v6/Makefile')

diff --git a/verilog/alu/v6/Makefile b/verilog/alu/v6/Makefile
index 437e09f..02598ac 100644
--- a/verilog/alu/v6/Makefile
+++ b/verilog/alu/v6/Makefile
@@ -32,7 +32,7 @@ simgate:
 	verilator -Wall --cc --exe --build tbalu.cpp synth_alu6.v --trace && ./obj_dir/Valu6 > out
 
 simclean:
-	rm -rf obj_dir/* out
+	rm -rf obj_dir/* out waveform.vcd
 
 clean:
 	$(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu
-- 
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