From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/alu/v6/alu6.v | 30 ------------------------------ 1 file changed, 30 deletions(-) delete mode 100644 verilog/alu/v6/alu6.v (limited to 'verilog/alu/v6/alu6.v') diff --git a/verilog/alu/v6/alu6.v b/verilog/alu/v6/alu6.v deleted file mode 100644 index 2f0f00c..0000000 --- a/verilog/alu/v6/alu6.v +++ /dev/null @@ -1,30 +0,0 @@ -`default_nettype none -`timescale 1us/1ns - -`include "aluOp.vh" - -module alu6 -( -input wire [31:0] alu_in_1, -input wire[31:0] alu_in_2, -input wire[3:0] alu_op_i, -output wire[31:0] alu_output -); - -wire [31:0] complement2 = ~alu_in_2 + 1'b1; -wire [31:0] sum = alu_in_1 + (alu_op_i[3] | (alu_op_i[1] & ~alu_op_i[0]) == 1'b1 ? complement2 : alu_in_2); -wire [31:0] right = alu_in_1 >> alu_in_2[5:0] | (alu_op_i[3] == 0 ? 32'b0 : - (32'hFFFFFFFF << (alu_in_2[31] == 1'b1 ? 5'b0 : {~alu_in_2[4] , ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]}))); - -assign alu_output = - alu_op_i[2:0] == `ADDSUB ? sum : - alu_op_i[2:0] == `XOR ? alu_in_1 ^ alu_in_2 : - alu_op_i[2:0] == `OR ? alu_in_1 | alu_in_2 : - alu_op_i[2:0] == `AND ? alu_in_1 & alu_in_2 : - alu_op_i[2:0] == `SLL ? alu_in_2[6] == 1 ? 32'b0 : alu_in_1 << alu_in_2[5:0] : - alu_op_i[2:0] == `SR ? right : - alu_op_i[2:0] == `SLT ? {31'b0, sum[31]} : - alu_op_i[2:0] == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : - 32'b0; -endmodule - -- cgit v1.2.3