From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001
From: Joshua Yun <jjyun4@illinois.edu>
Date: Mon, 28 Aug 2023 14:42:23 -0500
Subject: Added new riscv processor design into git repo

---
 verilog/alu/v6/aluOp.h | 16 ----------------
 1 file changed, 16 deletions(-)
 delete mode 100644 verilog/alu/v6/aluOp.h

(limited to 'verilog/alu/v6/aluOp.h')

diff --git a/verilog/alu/v6/aluOp.h b/verilog/alu/v6/aluOp.h
deleted file mode 100644
index 999dac2..0000000
--- a/verilog/alu/v6/aluOp.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef ALU_OP
-#define ALU_OP
-
-#define ADD             0
-#define SUB             8
-#define XOR             4
-#define OR              6
-#define AND             7
-#define SLL             1
-#define SRL             5
-#define SRA             13
-#define SLT             2
-#define SLTU            3
-#define NONE            15
-
-#endif
-- 
cgit v1.2.3