From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 14 May 2022 23:30:38 -0500 Subject: Verilog update --- verilog/alu/v6/aluOp.vh | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 verilog/alu/v6/aluOp.vh (limited to 'verilog/alu/v6/aluOp.vh') diff --git a/verilog/alu/v6/aluOp.vh b/verilog/alu/v6/aluOp.vh new file mode 100644 index 0000000..0e8c41a --- /dev/null +++ b/verilog/alu/v6/aluOp.vh @@ -0,0 +1,14 @@ +`ifndef ALU_OP +`define ALU_OP +// 1st bit that is no longer there == SUB/SRA/NONE +`define ADDSUB 3'b000 +`define XOR 3'b100 +`define OR 3'b110 +`define AND 3'b111 +`define SLL 3'b001 +`define SR 3'b101 +`define SLT 3'b010 +`define SLTU 3'b011 +`define NONE 3'b111 + +`endif -- cgit v1.2.3