From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001
From: Joshua Yun <jjyun4@illinois.edu>
Date: Mon, 28 Aug 2023 14:42:23 -0500
Subject: Added new riscv processor design into git repo

---
 verilog/alu/v6/aluOp.vh | 14 --------------
 1 file changed, 14 deletions(-)
 delete mode 100644 verilog/alu/v6/aluOp.vh

(limited to 'verilog/alu/v6/aluOp.vh')

diff --git a/verilog/alu/v6/aluOp.vh b/verilog/alu/v6/aluOp.vh
deleted file mode 100644
index 0e8c41a..0000000
--- a/verilog/alu/v6/aluOp.vh
+++ /dev/null
@@ -1,14 +0,0 @@
-`ifndef ALU_OP
-`define ALU_OP
-// 1st bit that is no longer there == SUB/SRA/NONE
-`define ADDSUB          3'b000 
-`define XOR             3'b100
-`define OR              3'b110
-`define AND             3'b111
-`define SLL             3'b001
-`define SR              3'b101
-`define SLT             3'b010
-`define SLTU            3'b011
-`define NONE            3'b111
-
-`endif
-- 
cgit v1.2.3