From 7a8afb2b6659f88881139fcbcb02de5476952152 Mon Sep 17 00:00:00 2001 From: joshua Date: Mon, 16 May 2022 11:00:23 -0400 Subject: Yes --- verilog/alu/v6/obj_dir/Valu6.h | 111 +++++++++++++++-------------------------- 1 file changed, 41 insertions(+), 70 deletions(-) (limited to 'verilog/alu/v6/obj_dir/Valu6.h') diff --git a/verilog/alu/v6/obj_dir/Valu6.h b/verilog/alu/v6/obj_dir/Valu6.h index 9cddec9..b7d0b23 100644 --- a/verilog/alu/v6/obj_dir/Valu6.h +++ b/verilog/alu/v6/obj_dir/Valu6.h @@ -1,59 +1,56 @@ // Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Primary design header +// DESCRIPTION: Verilator output: Primary model header // // This header should be included by all source files instantiating the design. // The class here is then constructed to instantiate the design. // See the Verilator manual for examples. -#ifndef _VALU6_H_ -#define _VALU6_H_ // guard +#ifndef VERILATED_VALU6_H_ +#define VERILATED_VALU6_H_ // guard -#include "verilated_heavy.h" - -//========== +#include "verilated.h" class Valu6__Syms; -class Valu6_VerilatedVcd; - +class Valu6___024root; +class VerilatedVcdC; -//---------- +// This class is the main interface to the Verilated model +class Valu6 VL_NOT_FINAL { + private: + // Symbol table holding complete model state (owned by this class) + Valu6__Syms* const vlSymsp; -VL_MODULE(Valu6) { public: - + // PORTS // The application code writes and reads these signals to // propagate new values into/out from the Verilated model. - VL_IN8(alu_op_i,3,0); - VL_IN(alu_in_1,31,0); - VL_IN(alu_in_2,31,0); - VL_OUT(alu_output,31,0); - - // LOCAL SIGNALS - // Internals; generally not touched by application code - IData/*31:0*/ alu6__DOT__sum; - - // LOCAL VARIABLES - // Internals; generally not touched by application code - CData/*0:0*/ __Vm_traceActivity[1]; - - // INTERNAL VARIABLES - // Internals; generally not touched by application code - Valu6__Syms* __VlSymsp; // Symbol table - + VL_IN8(&alu_op_i,3,0); + VL_IN(&alu_in_1,31,0); + VL_IN(&alu_in_2,31,0); + VL_OUT(&alu_output,31,0); + + // CELLS + // Public to allow access to /* verilator public */ items. + // Otherwise the application code can consider these internals. + + // Root instance pointer to allow access to model internals, + // including inlined /* verilator public_flat_* */ items. + Valu6___024root* const rootp; + // CONSTRUCTORS - private: - VL_UNCOPYABLE(Valu6); ///< Copying not allowed - public: /// Construct the model; called by application code - /// The special name may be used to make a wrapper with a + /// If contextp is null, then the model will use the default global context + /// If name is "", then makes a wrapper with a /// single model invisible with respect to DPI scope names. - Valu6(const char* name = "TOP"); + explicit Valu6(VerilatedContext* contextp, const char* name = "TOP"); + explicit Valu6(const char* name = "TOP"); /// Destroy the model; called (often implicitly) by application code - ~Valu6(); - /// Trace signals in the model; called by application code - void trace(VerilatedVcdC* tfp, int levels, int options = 0); - + virtual ~Valu6(); + private: + VL_UNCOPYABLE(Valu6); ///< Copying not allowed + + public: // API METHODS /// Evaluate the model. Application must call when inputs change. void eval() { eval_step(); } @@ -64,39 +61,13 @@ VL_MODULE(Valu6) { void eval_end_step() {} /// Simulation complete, run final blocks. Application must call on completion. void final(); - - // INTERNAL METHODS - static void _eval_initial_loop(Valu6__Syms* __restrict vlSymsp); - void __Vconfigure(Valu6__Syms* symsp, bool first); - private: - static QData _change_request(Valu6__Syms* __restrict vlSymsp); - static QData _change_request_1(Valu6__Syms* __restrict vlSymsp); - public: - static void _combo__TOP__1(Valu6__Syms* __restrict vlSymsp); - private: - void _ctor_var_reset() VL_ATTR_COLD; - public: - static void _eval(Valu6__Syms* __restrict vlSymsp); - private: -#ifdef VL_DEBUG - void _eval_debug_assertions(); -#endif // VL_DEBUG - public: - static void _eval_initial(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; - static void _eval_settle(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; - private: - static void traceChgSub0(void* userp, VerilatedVcd* tracep); - static void traceChgTop0(void* userp, VerilatedVcd* tracep); - static void traceCleanup(void* userp, VerilatedVcd* /*unused*/); - static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD; + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + /// Return current simulation context for this model. + /// Used to get to e.g. simulation time via contextp()->time() + VerilatedContext* contextp() const; + /// Retrieve name of this model instance (as passed to constructor). + const char* name() const; } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); -//---------- - - #endif // guard -- cgit v1.2.3