From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 14 May 2022 23:30:38 -0500 Subject: Verilog update --- verilog/alu/v6/obj_dir/Valu6.h | 102 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 verilog/alu/v6/obj_dir/Valu6.h (limited to 'verilog/alu/v6/obj_dir/Valu6.h') diff --git a/verilog/alu/v6/obj_dir/Valu6.h b/verilog/alu/v6/obj_dir/Valu6.h new file mode 100644 index 0000000..9cddec9 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6.h @@ -0,0 +1,102 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VALU6_H_ +#define _VALU6_H_ // guard + +#include "verilated_heavy.h" + +//========== + +class Valu6__Syms; +class Valu6_VerilatedVcd; + + +//---------- + +VL_MODULE(Valu6) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(alu_op_i,3,0); + VL_IN(alu_in_1,31,0); + VL_IN(alu_in_2,31,0); + VL_OUT(alu_output,31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + IData/*31:0*/ alu6__DOT__sum; + + // LOCAL VARIABLES + // Internals; generally not touched by application code + CData/*0:0*/ __Vm_traceActivity[1]; + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + Valu6__Syms* __VlSymsp; // Symbol table + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Valu6); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + Valu6(const char* name = "TOP"); + /// Destroy the model; called (often implicitly) by application code + ~Valu6(); + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval() { eval_step(); } + /// Evaluate when calling multiple units/models per time step. + void eval_step(); + /// Evaluate at end of a timestep for tracing, when using eval_step(). + /// Application must call after all eval() and before time changes. + void eval_end_step() {} + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + static void _eval_initial_loop(Valu6__Syms* __restrict vlSymsp); + void __Vconfigure(Valu6__Syms* symsp, bool first); + private: + static QData _change_request(Valu6__Syms* __restrict vlSymsp); + static QData _change_request_1(Valu6__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__1(Valu6__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void _eval(Valu6__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _eval_settle(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; + private: + static void traceChgSub0(void* userp, VerilatedVcd* tracep); + static void traceChgTop0(void* userp, VerilatedVcd* tracep); + static void traceCleanup(void* userp, VerilatedVcd* /*unused*/); + static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD; +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +//---------- + + +#endif // guard -- cgit v1.2.3