From 7a8afb2b6659f88881139fcbcb02de5476952152 Mon Sep 17 00:00:00 2001 From: joshua Date: Mon, 16 May 2022 11:00:23 -0400 Subject: Yes --- verilog/alu/v6/obj_dir/Valu6__Syms.cpp | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'verilog/alu/v6/obj_dir/Valu6__Syms.cpp') diff --git a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp index c9b82af..fe8a162 100644 --- a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp +++ b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp @@ -3,25 +3,24 @@ #include "Valu6__Syms.h" #include "Valu6.h" - - +#include "Valu6___024root.h" // FUNCTIONS Valu6__Syms::~Valu6__Syms() { } -Valu6__Syms::Valu6__Syms(Valu6* topp, const char* namep) - // Setup locals - : __Vm_namep(namep) - , __Vm_activity(false) - , __Vm_baseCode(0) - , __Vm_didInit(false) - // Setup submodule names +Valu6__Syms::Valu6__Syms(VerilatedContext* contextp, const char* namep,Valu6* modelp) + : VerilatedSyms{contextp} + // Setup internal state of the Syms class + , __Vm_modelp{modelp} + // Setup module instances + , TOP{this, namep} { - // Pointer to top level - TOPp = topp; + // Configure time unit / time precision + _vm_contextp__->timeunit(-6); + _vm_contextp__->timeprecision(-9); // Setup each module's pointers to their submodules // Setup each module's pointer back to symbol table (for public functions) - TOPp->__Vconfigure(this, true); + TOP.__Vconfigure(true); } -- cgit v1.2.3