From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 14 May 2022 23:30:38 -0500 Subject: Verilog update --- verilog/alu/v6/obj_dir/Valu6__Syms.cpp | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 verilog/alu/v6/obj_dir/Valu6__Syms.cpp (limited to 'verilog/alu/v6/obj_dir/Valu6__Syms.cpp') diff --git a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp new file mode 100644 index 0000000..c9b82af --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp @@ -0,0 +1,27 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Valu6__Syms.h" +#include "Valu6.h" + + + +// FUNCTIONS +Valu6__Syms::~Valu6__Syms() +{ +} + +Valu6__Syms::Valu6__Syms(Valu6* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_activity(false) + , __Vm_baseCode(0) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); +} -- cgit v1.2.3