From 7a8afb2b6659f88881139fcbcb02de5476952152 Mon Sep 17 00:00:00 2001 From: joshua Date: Mon, 16 May 2022 11:00:23 -0400 Subject: Yes --- verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp') diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp index b2933ac..71768c8 100644 --- a/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp +++ b/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp @@ -21,17 +21,15 @@ void Valu6___024root__trace_chg_sub_0(Valu6___024root* vlSelf, VerilatedVcd* tra Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_chg_sub_0\n"); ); // Init - vluint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode + 1); + uint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode + 1); // Body tracep->chgIData(oldp+0,(vlSelf->alu_in_1),32); tracep->chgIData(oldp+1,(vlSelf->alu_in_2),32); tracep->chgCData(oldp+2,(vlSelf->alu_op_i),4); tracep->chgIData(oldp+3,(vlSelf->alu_output),32); - tracep->chgIData(oldp+4,(vlSelf->debugsum),32); - tracep->chgCData(oldp+5,(vlSelf->debugop),4); - tracep->chgIData(oldp+6,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); - tracep->chgIData(oldp+7,(vlSelf->alu6__DOT__sum),32); - tracep->chgIData(oldp+8,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) + tracep->chgIData(oldp+4,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); + tracep->chgIData(oldp+5,(vlSelf->alu6__DOT__sum),32); + tracep->chgIData(oldp+6,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) ? (vlSelf->alu_in_1 >> (0x3fU & vlSelf->alu_in_2)) : 0U) | ((8U & (IData)(vlSelf->alu_op_i)) -- cgit v1.2.3