From 7a8afb2b6659f88881139fcbcb02de5476952152 Mon Sep 17 00:00:00 2001 From: joshua Date: Mon, 16 May 2022 11:00:23 -0400 Subject: Yes --- verilog/alu/v6/obj_dir/Valu6___024root.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'verilog/alu/v6/obj_dir/Valu6___024root.h') diff --git a/verilog/alu/v6/obj_dir/Valu6___024root.h b/verilog/alu/v6/obj_dir/Valu6___024root.h index f568bf9..968e6b6 100644 --- a/verilog/alu/v6/obj_dir/Valu6___024root.h +++ b/verilog/alu/v6/obj_dir/Valu6___024root.h @@ -13,23 +13,21 @@ VL_MODULE(Valu6___024root) { // DESIGN SPECIFIC STATE VL_IN8(alu_op_i,3,0); - VL_OUT8(debugop,3,0); VL_IN(alu_in_1,31,0); VL_IN(alu_in_2,31,0); VL_OUT(alu_output,31,0); - VL_OUT(debugsum,31,0); IData/*31:0*/ alu6__DOT__sum; // INTERNAL VARIABLES - Valu6__Syms* vlSymsp; // Symbol table + Valu6__Syms* const vlSymsp; // CONSTRUCTORS - Valu6___024root(const char* name); + Valu6___024root(Valu6__Syms* symsp, const char* name); ~Valu6___024root(); VL_UNCOPYABLE(Valu6___024root); // INTERNAL METHODS - void __Vconfigure(Valu6__Syms* symsp, bool first); + void __Vconfigure(bool first); } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); -- cgit v1.2.3