From 7a8afb2b6659f88881139fcbcb02de5476952152 Mon Sep 17 00:00:00 2001 From: joshua Date: Mon, 16 May 2022 11:00:23 -0400 Subject: Yes --- verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp | 2 -- 1 file changed, 2 deletions(-) (limited to 'verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp') diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp index 896483f..88991f6 100644 --- a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp +++ b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp @@ -37,7 +37,5 @@ VL_ATTR_COLD void Valu6___024root___ctor_var_reset(Valu6___024root* vlSelf) { vlSelf->alu_in_2 = VL_RAND_RESET_I(32); vlSelf->alu_op_i = VL_RAND_RESET_I(4); vlSelf->alu_output = VL_RAND_RESET_I(32); - vlSelf->debugsum = VL_RAND_RESET_I(32); - vlSelf->debugop = VL_RAND_RESET_I(4); vlSelf->alu6__DOT__sum = VL_RAND_RESET_I(32); } -- cgit v1.2.3