From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001
From: joshua <joshua@fedora.framework>
Date: Sat, 14 May 2022 23:30:38 -0500
Subject: Verilog update

---
 verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp

(limited to 'verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp')

diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp
new file mode 100644
index 0000000..9918041
--- /dev/null
+++ b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp
@@ -0,0 +1,25 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Valu6.h for the primary calling header
+
+#include "verilated.h"
+
+#include "Valu6__Syms.h"
+#include "Valu6___024root.h"
+
+void Valu6___024root___ctor_var_reset(Valu6___024root* vlSelf);
+
+Valu6___024root::Valu6___024root(const char* _vcname__)
+    : VerilatedModule(_vcname__)
+ {
+    // Reset structure values
+    Valu6___024root___ctor_var_reset(this);
+}
+
+void Valu6___024root::__Vconfigure(Valu6__Syms* _vlSymsp, bool first) {
+    if (false && first) {}  // Prevent unused
+    this->vlSymsp = _vlSymsp;
+}
+
+Valu6___024root::~Valu6___024root() {
+}
-- 
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