From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001
From: Joshua Yun <jjyun4@illinois.edu>
Date: Mon, 28 Aug 2023 14:42:23 -0500
Subject: Added new riscv processor design into git repo

---
 verilog/alu/v6/shifter.v | 42 ------------------------------------------
 1 file changed, 42 deletions(-)
 delete mode 100644 verilog/alu/v6/shifter.v

(limited to 'verilog/alu/v6/shifter.v')

diff --git a/verilog/alu/v6/shifter.v b/verilog/alu/v6/shifter.v
deleted file mode 100644
index 7030a1c..0000000
--- a/verilog/alu/v6/shifter.v
+++ /dev/null
@@ -1,42 +0,0 @@
-`default_nettype none
-`timescale 1us/1ns
-
-module rightshifter
-(
-	input wire [31:0] shift,
-	input wire [31:0] number,
-	output wire [31:0] shifted
-);
-
-always @ (*)
-begin
-	if (number[5] == 1'b1)
-	begin
-		shifted = {32{number[31]}};
-	end
-	else
-	begin
-		if (number[4] == 1'b1)
-		begin
-			shifted = {{16{number[31]}}, number[31:16]}
-		end
-		if (number[3] == 1'b1)
-		begin
-			shifted = {{8{number[31]}}, number[31:8]}
-		end
-		if (number[2] == 1'b1)
-		begin
-			shifted = {{4{number[31]}}, number[31:4]}
-		end
-		if (number[1] == 1'b1)
-		begin
-			shifted = {{2{number[31]}}, number[31:2]}
-		end
-		if (number[0] == 1'b1)
-		begin
-			shifted = {number[31], number[31:1]}
-		end
-	end
-end
-
-endmodule
-- 
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