From b8936029065835366e9e057a219c0c5194db8662 Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 14 May 2022 23:30:38 -0500 Subject: Verilog update --- verilog/alu/v6/synth_alu6.v alu6.blif | 1 + 1 file changed, 1 insertion(+) create mode 100644 verilog/alu/v6/synth_alu6.v alu6.blif (limited to 'verilog/alu/v6/synth_alu6.v alu6.blif') diff --git a/verilog/alu/v6/synth_alu6.v alu6.blif b/verilog/alu/v6/synth_alu6.v alu6.blif new file mode 100644 index 0000000..8186d4c --- /dev/null +++ b/verilog/alu/v6/synth_alu6.v alu6.blif @@ -0,0 +1 @@ +# Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) -- cgit v1.2.3