From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/alu/v6/synth_alu6.v alu6.blif | 1 - 1 file changed, 1 deletion(-) delete mode 100644 verilog/alu/v6/synth_alu6.v alu6.blif (limited to 'verilog/alu/v6/synth_alu6.v alu6.blif') diff --git a/verilog/alu/v6/synth_alu6.v alu6.blif b/verilog/alu/v6/synth_alu6.v alu6.blif deleted file mode 100644 index 8186d4c..0000000 --- a/verilog/alu/v6/synth_alu6.v alu6.blif +++ /dev/null @@ -1 +0,0 @@ -# Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) -- cgit v1.2.3