From d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c Mon Sep 17 00:00:00 2001
From: joshua <joshua@joshuayun.com>
Date: Sat, 16 Apr 2022 23:00:55 -0500
Subject: Added pdfs and more alu stuff

---
 verilog/alu/alu.v    | 26 ++++++++++++++++++++++++++
 verilog/alu/aluOp.vh | 14 ++++++++++++++
 verilog/alu/tbalu.v  | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 90 insertions(+)
 create mode 100644 verilog/alu/alu.v
 create mode 100644 verilog/alu/aluOp.vh
 create mode 100644 verilog/alu/tbalu.v

(limited to 'verilog/alu')

diff --git a/verilog/alu/alu.v b/verilog/alu/alu.v
new file mode 100644
index 0000000..3a4213a
--- /dev/null
+++ b/verilog/alu/alu.v
@@ -0,0 +1,26 @@
+`include "aluOp.vh"
+
+module riscv_alu
+(
+input wire [31:0] alu_in_1,
+input wire[31:0] alu_in_2,
+input wire[3:0] alu_op_i,
+output wire[31:0] alu_output
+);
+
+
+wire diff = alu_in_1 - alu_in_2;
+wire ones = 32'hFFFFFFFF;
+
+assign alu_output = alu_op_i == ADD ? alu_in_1 + alu_in_2 :
+	alu_op_i == SUB ?  diff :
+	alu_op_i == XOR ? alu_in_1 ^ alu_in_2 :
+	alu_op_i == OR ? alu_in_1 | alu_in_2 :
+	alu_op_i == AND ? alu_in_1 & alu_in_2 :
+	alu_op_i == SLL ? alu_in_1 << alu_in_2 :
+	alu_op_i == SRL ? alu_in_1 >> alu_in_2 :
+	alu_op_i == SLT ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) :
+	alu_op_i == NONE ? alu_in_1 : 32'b0 :
+	alu_op_i == SLTU ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 0 ? 0 : 1) : (alu_in_1[31] == 1 ? 1 : 0) ) :
+	alu_op_i == SRA ? alu_in_1[31] == 0 ? alu_in_1 >> alu_in_2 :  ;
+endmodule
diff --git a/verilog/alu/aluOp.vh b/verilog/alu/aluOp.vh
new file mode 100644
index 0000000..c67cd33
--- /dev/null
+++ b/verilog/alu/aluOp.vh
@@ -0,0 +1,14 @@
+`ifndef ALU_OP
+`define ALU_OP
+`define ADD             4'b0000
+`define SUB             4'b1000
+`define XOR             4'b0100
+`define OR              4'b0110
+`define AND             4'b0111
+`define SLL             4'b0001
+`define SRL             4'b0101
+`define SRA             4'b1101
+`define SLT             4'b0010
+`define SLTU            4'b0011
+`define NONE            4'h1111
+`endif
diff --git a/verilog/alu/tbalu.v b/verilog/alu/tbalu.v
new file mode 100644
index 0000000..7ffc8bf
--- /dev/null
+++ b/verilog/alu/tbalu.v
@@ -0,0 +1,50 @@
+`timescale 1us/1ns
+
+`include "alu_ops.vh"
+`include "alu.v"
+
+module tbalu;
+
+reg [31:0] in1,in2;
+wire [31:0] out;
+reg [3:0] op;
+
+alu alu0 (in1, in2,op, out);
+
+initial begin
+	in1=-32'b1;
+	in2=32'b1;
+	op=`ADD;
+	#5
+	$display("\nPlus:\t\t %d %32b + %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`SUB;
+	#5
+	$display("\nMinus:\t\t %d %32b - %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`XOR;
+	#5
+	$display("\nXor:\t\t %d %32b ^ %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`OR;
+	#5
+	$display("\nOr:\t\t %d %32b | %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`AND;
+	#5
+	$display("\nAnd:\t\t %d %32b & %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`SLL;
+	#5
+	$display("\nLeft Logical:\t %d %32b << %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`SRL;
+	#5
+	$display("\nRight Logical:\t %d %32b >> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`SRA;
+	#5
+	$display("\nRight Arith:\t %d %32b >>> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`SLT;
+	#5
+	$display("\nSet Less:\t %d %32b < %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	op=`SLTU;
+	#5
+	$display("\nSet Less U:\t %d %32b < U %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out);
+	$finish;
+end
+
+endmodule
-- 
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