From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/computer-architecture-parts.drawio | 1 + 1 file changed, 1 insertion(+) create mode 100644 verilog/computer-architecture-parts.drawio (limited to 'verilog/computer-architecture-parts.drawio') diff --git a/verilog/computer-architecture-parts.drawio b/verilog/computer-architecture-parts.drawio new file mode 100644 index 0000000..71c8870 --- /dev/null +++ b/verilog/computer-architecture-parts.drawio @@ -0,0 +1 @@ +[{"xml":"jVLLsqIwFPwaqmZ2GBRwKQ9REBXBB+xQIiEQCBAF/fqJ4p1bs7hVs0iq050+p+qcFiSd9FYTU+RWCSwEyRQkvakqNiDS67AoBCBmiSAZAgAiPwKY/6CO3qpI4waW7H8MYDDc4+IGB2YgWvYoPkSLYvqCLYPlJSt+NVGww+0yNc0jr4uKxPAO/TVIrlNjRMvVzkKzQyRxaTqhXrw+EoZuIvYj+GwXxC50uMnPwLMR0xdq/tSO+yW9Y1ft5xnZ36u9vNuIeRk5B3TD4/Gm056kOpm5E2m0c8rLTUKW0hEBaAqKjmDthdmjx+o4eSo6NZzQl1S80l/tC3k5zyRr5fQdSs2bgjOKTpOtJnNN1efiNFU9OSxknMttsPJZvLifXa5F+Oo+yuY6as3VGIRNc3S3u06JH7WszHjfdb3gt2i39T5xODIPlX2yZzQMdFNduqc2qKfEBBNeamTkS9XFinme+efUxp44p+ftM/JqKyF6zc25ZAQgDte9wg5jfD3pmveaumT8FiStQxmDPo0vr/F3PCOcQ4zwkBgjDj+rgw2D/Y/rf1Of3VuwIpA1D/6lyxKGhh/ykBARwSxFX65PbMS4HYj0r/U7TBx88vT1/M7tW/sn1n8A","w":60,"h":120,"aspect":"fixed","title":"alu/adder"},{"xml":"jVNfc6IwHPw0zNy9SVItPpIgFSWgglp5408kaaMIRIJ++qbFu849dOYeMrPZ324IsxsD4lP/0qQXRqqCCgPODIibqpIDOvWYCmGAES8M6BgAjPQygPvD1Pyaji5pQ8/yfwxgMHSpuNKBGYhW3sSDaFl6+YStpOeci19N8rrJKlK6Xnpk4uoQt+jcZzpFz7v2XXhKBY18PlAMC8Qm4j0+QD/0ewMgfQumSAkkD6cbtYF4Pnmzyws5Jt3cnOJXQtcgmUD/God3mwNxV5XJxHSMij5HM7YjNMi9YPna65OQJS3iADNtkmiOl2ZbdfdodVCLcX7kd4X9EdSfc2uMdtFqo/WcBRDO4sw7dN5yzK3r543GNVoAGk1VmIXWLXblEacQ+XHSanP2lHXRPOT9PMm2MDuWRyW2+22Vgf3qvDmXIGh7+6RPSeOVli9zbJm7rNaEO3uf+QIXhcbQWjzFSMRjLVHOem17ETbTeq+TQmQ/qcN8XTMf1bZY3DCemVZi84kYodZ5cWDA7Tpxk6kZ2fN6Aj2SxJ4f6N9xN/tIx4T8t5ZsE7LPHBmTU1fqjJ3fBkSKcUmjS5p/Bqd0uzTH5EnXyzE1fIROG0n7H4vzRT1a80KrE5XNTUsULyQbFOOhWyNGeckeLuvBpe2wL/86v1uowaOIf7bfhf+a/fMePgA=","w":50,"h":80,"aspect":"fixed","title":"2:1 Mux"},{"xml":"jVPLsqIwEP0aqmZ2Coi6VEAGBK+g8nAXSCBAeFyIBvz6ieLMrVncqlmk6vTpPklX94kgqdVgdKDFTgMRESRdkNSuaeiEqkFFhAjiLIeCpAmiOONHEHffZOev7KwFHarp/wjESXAH5IYmZiJ6OpI30WPQPmFPUZ3k5Ed3Db24N7OdCVJMbpqjwTsRFUHcbtfgQaLC3RyOdBlCEBSoMcy+0ty6tocV7wIzxw07YlB9E8Uu5owpM7pPLgGXK6kbsjWU/c8mjTKIr37+OW6aB7k98OKY8ApXx9A9PGvLJVnKJw7kgl8CB+UOgDlzQXyyya+Vwprz5cO6PnsaMOx3QbQYkwPVCntzfkQsrEy9A4stly5H55iN5plDFwaWorU4NBxCt3suFhu64Ing/kHg+uAFSNICO8tqI2h9NT/tGaWe/2xMF40Ln9U2MtOhjMjAalmzFEvN25XsPebJGh8d5PShfXPtjerp5Q1UfpIWh9tYV9bcs1Xfc8j+tMKDClBJW5wzM1bRqYojSi07eOw/i2ztDXrKYFnkJX/LXJaalHEQS3zyB42tU7QJfwrSluGcolMLkufaGPcW5zCtuLm0OYfvlaOOouFb27yot2cM1FSIdiMvYTmkeKqQF5MKozzDb9VqctsM9FOc/VV+eZCDtw3/hF92f+X++Q2/AQ==","w":45,"h":80,"aspect":"fixed","title":"(Alt) 2:1 Mux"}] \ No newline at end of file -- cgit v1.2.3