From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/data_mem.mem | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 verilog/data_mem.mem (limited to 'verilog/data_mem.mem') diff --git a/verilog/data_mem.mem b/verilog/data_mem.mem new file mode 100644 index 0000000..d3d39ad --- /dev/null +++ b/verilog/data_mem.mem @@ -0,0 +1,59 @@ +00010203 // 0x00 +04050607 // 0x04 +08090A0B // 0x08 +0C0D0E0F // 0x0C +10111213 // 0x10 +14151617 // 0x14 +18191A1B // 0x08 +1C1D1E1F // 0x1C +00000000 // Zero Buffer +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 -- cgit v1.2.3