From 9dc6d7180438031d25daf6a68a3959c3cfa9312d Mon Sep 17 00:00:00 2001 From: joshua Date: Tue, 14 Dec 2021 01:46:40 -0600 Subject: Initial Commit --- verilog/fpu/compile | 4 ++++ 1 file changed, 4 insertions(+) create mode 100755 verilog/fpu/compile (limited to 'verilog/fpu/compile') diff --git a/verilog/fpu/compile b/verilog/fpu/compile new file mode 100755 index 0000000..08b3b83 --- /dev/null +++ b/verilog/fpu/compile @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog fpu_bench.v +vvp a.out -- cgit v1.2.3