From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/immediate.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 verilog/immediate.v (limited to 'verilog/immediate.v') diff --git a/verilog/immediate.v b/verilog/immediate.v new file mode 100644 index 0000000..37111da --- /dev/null +++ b/verilog/immediate.v @@ -0,0 +1,20 @@ +`default_nettype none +`timescale 1ns/1ps + +module immediate +( + input wire [31:7] instr, + input wire i,u,j,b, + output wire [31:0] imm +); + +// Note, can get rid of S signal if needed +assign imm[31] = instr[31]; +assign imm[30:20] = u ? instr[30:20] : {11{instr[31]}}; +assign imm[19:12] = (u|j) ? instr[19:12] : {8{instr[31]}}; +assign imm[11] = ~u & (b ? instr[7] : (j ? instr[20] : instr[31])); +assign imm[10:5] = {6{~u}} & instr[30:25]; +assign imm[4:1] = {4{~u}} & (i|j ? instr[24:21] : instr[11:8]); +assign imm[0] = ~(u|j|b) & (i ? instr[20] : instr[7]); + +endmodule -- cgit v1.2.3