From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/instr_mem.mem | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 verilog/instr_mem.mem (limited to 'verilog/instr_mem.mem') diff --git a/verilog/instr_mem.mem b/verilog/instr_mem.mem new file mode 100644 index 0000000..bd4c611 --- /dev/null +++ b/verilog/instr_mem.mem @@ -0,0 +1,55 @@ +01000093 +01234137 +00001197 +02000213 +03000293 +00000013 // NOP Buffer +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 +00000013 -- cgit v1.2.3