From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/pc.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 verilog/pc.v (limited to 'verilog/pc.v') diff --git a/verilog/pc.v b/verilog/pc.v new file mode 100644 index 0000000..a7c6b6d --- /dev/null +++ b/verilog/pc.v @@ -0,0 +1,20 @@ +`default_nettype none +`timescale 1ns/1ps + +module pc +( + input wire we, clk, rst, + input wire [31:0] pc_new, + output reg [31:0] pc +); + +always @ (posedge clk or posedge rst) begin + if (rst) begin + pc <= 0; + end + else if (we) begin + pc <= pc_new; + end +end + +endmodule -- cgit v1.2.3