From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/regfile.v | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 verilog/regfile.v (limited to 'verilog/regfile.v') diff --git a/verilog/regfile.v b/verilog/regfile.v new file mode 100644 index 0000000..56d107f --- /dev/null +++ b/verilog/regfile.v @@ -0,0 +1,36 @@ +`default_nettype none +`timescale 1ns/1ps + +module regfile ( + input wire clk, we, + input wire [4:0] r1addr, r2addr, waddr, + input wire [31:0] wdata, + output wire [31:0] r1data, r2data +); + +reg [31:0] registers [1:31]; + +/* Async Read on second half of cycle */ +assign r1data = registers[r1addr]; +assign r2data = registers[r2addr]; + +/* Async write at the beginning of the cycle */ +always @ (negedge clk) begin + if (we == 1'b1 && waddr != 5'b0) begin + registers[waddr] <= wdata; + end +end + +// Debugging Access Functions +`ifdef verilator + export "DPI-C" task get_reg_value; + task get_reg_value; + input bit [4:0] get_addr; + output bit [31:0] reg_val; + begin + reg_val = registers[get_addr]; + end + endtask +`endif + +endmodule -- cgit v1.2.3