From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Mon, 28 Aug 2023 14:42:23 -0500 Subject: Added new riscv processor design into git repo --- verilog/register/registers.v | 22 ---------------------- 1 file changed, 22 deletions(-) delete mode 100644 verilog/register/registers.v (limited to 'verilog/register/registers.v') diff --git a/verilog/register/registers.v b/verilog/register/registers.v deleted file mode 100644 index f2dbb22..0000000 --- a/verilog/register/registers.v +++ /dev/null @@ -1,22 +0,0 @@ -module registers( - input wire writeEnable, - input wire clk, - input wire [31:0] addr1, - input wire [31:0] addr2, - input wire [31:0] addr3, - input wire [31:0] writeData, - output wire [31:0] readData1, - output wire [31:0] readData2 -); - -reg [31:0] register [0:31]; - -always @ (posedge clk) -begin - register[addr3] <= writeEnable ? writeData : register[addr3]; -end - -assign readData1 = register[addr1]; -assign readData2 = register[addr2]; - -endmodule -- cgit v1.2.3