From d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 16 Apr 2022 23:00:55 -0500 Subject: Added pdfs and more alu stuff --- verilog/register/registers.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 verilog/register/registers.v (limited to 'verilog/register/registers.v') diff --git a/verilog/register/registers.v b/verilog/register/registers.v new file mode 100644 index 0000000..f2dbb22 --- /dev/null +++ b/verilog/register/registers.v @@ -0,0 +1,22 @@ +module registers( + input wire writeEnable, + input wire clk, + input wire [31:0] addr1, + input wire [31:0] addr2, + input wire [31:0] addr3, + input wire [31:0] writeData, + output wire [31:0] readData1, + output wire [31:0] readData2 +); + +reg [31:0] register [0:31]; + +always @ (posedge clk) +begin + register[addr3] <= writeEnable ? writeData : register[addr3]; +end + +assign readData1 = register[addr1]; +assign readData2 = register[addr2]; + +endmodule -- cgit v1.2.3