From c1fa3c36da28e9e947f6279329c47777f31fe7a2 Mon Sep 17 00:00:00 2001
From: Joshua Yun <jjyun4@illinois.edu>
Date: Mon, 28 Aug 2023 14:42:23 -0500
Subject: Added new riscv processor design into git repo

---
 verilog/tbalu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 verilog/tbalu.h

(limited to 'verilog/tbalu.h')

diff --git a/verilog/tbalu.h b/verilog/tbalu.h
new file mode 100644
index 0000000..9e010e6
--- /dev/null
+++ b/verilog/tbalu.h
@@ -0,0 +1,15 @@
+#ifndef ALUOP
+#define ALUOP
+
+#define ADD             0b0000
+#define SUB             0b1000
+#define XOR             0b0010
+#define OR              0b0110
+#define AND             0b0111
+#define SLL             0b0001
+#define SRL             0b0101
+#define SRA             0b1101
+#define SLT             0b0010
+#define SLTU            0b0011
+
+#endif
-- 
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