/verilog/alu/v6/
../
LUTS
Makefile
alu6.blif
alu6.v
aluOp.h
aluOp.vh
crab.pcf
obj_dir
out
shifter.v
synth_alu6.v
synth_alu6.v alu6.blif
tbalu.cpp
waveform.vcd