Initial docker setup commit

7 files changed, 80 insertions, 0 deletions

diff --git a/tools/Dockerfile b/tools/Dockerfile
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+++ b/tools/Dockerfile
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+FROM verilator/verilator:latest
+
+# Install python3 + pip3 for fusesoc
+RUN apt-get update \
+    && DEBIAN_FRONTEND=noninteractive \
+    && apt-get install --no-install-recommends -y \
+                        python3 \
+                        python3-pip \
+                        vim \
+                        neovim \
+                        tmux \
+    && apt-get clean \
+    && rm -rf /var/lib/apt/lists/*
+
+RUN pip3 install --upgrade fusesoc 
+
+WORKDIR /work
+
+ENTRYPOINT [ "/bin/bash", "-l", "-c" ]
diff --git a/tools/config/README b/tools/config/README
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+++ b/tools/config/README
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+# Configuration files for your favorite programs
+Put all of your config files in here, if you want to add new programs, add new mounts to the docker compose and new programs to the docker file.
diff --git a/tools/config/nvim/.gitignore b/tools/config/nvim/.gitignore
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+++ b/tools/config/nvim/.gitignore
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+*
+!.gitignore
diff --git a/tools/config/tmux/.gitignore b/tools/config/tmux/.gitignore
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+++ b/tools/config/tmux/.gitignore
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+*
+!.gitignore
diff --git a/tools/devbox.sh b/tools/devbox.sh
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+++ b/tools/devbox.sh
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+docker compose run --rm dev_environment /bin/bash
diff --git a/tools/docker-compose.yml b/tools/docker-compose.yml
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+++ b/tools/docker-compose.yml
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+services:
+  dev_environment:
+    container_name: devbox
+    image: bingchao:latest
+
+    # Allow for interactive terminal
+    stdin_open: true
+    tty: true
+
+    # Mount to repository
+    volumes:
+      - ../:/work
+      - ./config/nvim:/root/.config/nvim
+      - ./config/tmux:/root/.config/tmux
+
diff --git a/top.core b/top.core
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+++ b/top.core
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+CAPI=2:
+name: bingchao:riscv:top
+description: Fully Linux Capable Processor
+
+filesets:
+  rtl:
+    files:
+      - rtl/top.sv
+      - rtl/top.svh:
+          is_include_file: true
+    file_type: systemVerilogSource
+
+  tb:
+    files:
+      - tb/top_tb.sv
+    file_type: systemVerilogSource
+
+targets:
+
+  default: &default
+    filesets:
+      - rtl
+    toplevel: top
+    parameters:
+      - clk_freq_hz
+
+    sim:
+      <<: *default
+      description: Simulate the design
+      default_tool: verilator
+      tools:
+        verilator:
+          verilator_options:
+        icarus:
+          iverilog_options:
+            - -g2012
+      parameters:
+        - pulses=10
+