chore: Merge branch 'joshua/fusesoc' into 'main'

Joshua/fusesoc

See merge request falsestatement/riscv_linux!4

5 files changed, 26 insertions, 20 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..a007fea
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+build/*
diff --git a/fusesoc.conf b/fusesoc.conf
new file mode 100644
index 0000000..e03e5a7
--- /dev/null
+++ b/fusesoc.conf
@@ -0,0 +1,6 @@
+[library.rtl]
+location = /work
+sync-uri = /work
+sync-type = local
+auto-sync = true
+
diff --git a/rtl/top.sv b/rtl/top.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/rtl/top.sv
diff --git a/tb/top_tb.sv b/tb/top_tb.sv
new file mode 100644
index 0000000..7643fbe
--- /dev/null
+++ b/tb/top_tb.sv
@@ -0,0 +1,7 @@
+module top_tb ();
+
+initial begin
+  $display("Hello World");
+end
+
+endmodule
diff --git a/top.core b/top.core
index e8a009d..db67ab4 100644
--- a/top.core
+++ b/top.core
@@ -1,13 +1,11 @@
 CAPI=2:
-name: bingchao:riscv:top
-description: Fully Linux Capable Processor
+name: riscv:cpu:top:1.0.0
+description: Top level module for RISC-V processor
 
 filesets:
   rtl:
     files:
       - rtl/top.sv
-      - rtl/top.svh:
-          is_include_file: true
     file_type: systemVerilogSource
 
   tb:
@@ -16,24 +14,18 @@ filesets:
     file_type: systemVerilogSource
 
 targets:
-
   default: &default
     filesets:
       - rtl
     toplevel: top
-    parameters:
-      - clk_freq_hz
-
-    sim:
-      <<: *default
-      description: Simulate the design
-      default_tool: verilator
-      tools:
-        verilator:
-          verilator_options:
-        icarus:
-          iverilog_options:
-            - -g2012
-      parameters:
-        - pulses=10
 
+  sim:
+    <<: *default
+    description: Run top level testbench
+    default_tool: verilator
+    filesets_append:
+      - tb
+    toplevel: top_tb
+    tools:
+      verilator:
+        mode: binary