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| author | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 23:09:39 -0500 |
|---|---|---|
| committer | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 23:09:39 -0500 |
| commit | 6bd9f4f7ab48576d3fda98bef915162a7436866d (patch) | |
| tree | a0af72467af1020f9e492b177e2d95ed8998d1dc /core/pkg | |
| parent | 59fd8c25ee1452452cb564d6fe4163b7a9394aef (diff) | |
| download | riscv-processor-6bd9f4f7ab48576d3fda98bef915162a7436866d.tar.gz | |
feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64
Diffstat (limited to 'core/pkg')
| -rw-r--r-- | core/pkg/riscv_types.sv | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/core/pkg/riscv_types.sv b/core/pkg/riscv_types.sv new file mode 100644 index 0000000..3d68331 --- /dev/null +++ b/core/pkg/riscv_types.sv @@ -0,0 +1,14 @@ +package riscv_types; + typedef enum logic [6:0] { + INSTR_TYPE_LUI = 7'b0110111, // U load upper immediate + INSTR_TYPE_AUIPC = 7'b0010111, // U add upper immediate PC + INSTR_TYPE_JAL = 7'b1101111, // J jump and link + INSTR_TYPE_JALR = 7'b1100111, // I jump and link register + INSTR_TYPE_BR = 7'b1100011, // B branch + INSTR_TYPE_LD = 7'b0000011, // I load + INSTR_TYPE_ST = 7'b0100011, // S store + INSTR_TYPE_IMM = 7'b0010011, // I arith ops with register/immediate operands + INSTR_TYPE_REG = 7'b0110011, // R arith ops with register operands + INSTR_TYPE_CSR = 7'b1110011 // I control and status register + } opcode_t; +endpackage |