initial commit

1 files changed, 40 insertions, 17 deletions

diff --git a/core/pkg/riscv_types.sv b/core/pkg/riscv_types.sv
index 48ca87b..59c1f74 100644
--- a/core/pkg/riscv_types.sv
+++ b/core/pkg/riscv_types.sv
@@ -1,14 +1,21 @@
 package riscv_types;
+  WORD_WIDTH = 32;
+  NUM_REG    = 32;
+  REG_IDX    = $clog2(NUM_REG);
+
+  //-----------------
+  // Decode Types
+  //-----------------
   typedef enum logic [6:0] {
-      INSTR_TYPE_LUI   = 7'b0110111, // U load upper immediate 
-      INSTR_TYPE_AUIPC = 7'b0010111, // U add upper immediate PC 
-      INSTR_TYPE_JAL   = 7'b1101111, // J jump and link 
-      INSTR_TYPE_JALR  = 7'b1100111, // I jump and link register 
-      INSTR_TYPE_BR    = 7'b1100011, // B branch 
-      INSTR_TYPE_LD    = 7'b0000011, // I load 
-      INSTR_TYPE_ST    = 7'b0100011, // S store 
-      INSTR_TYPE_IMM   = 7'b0010011, // I arith ops with register/immediate operands 
-      INSTR_TYPE_REG   = 7'b0110011, // R arith ops with register operands 
+      INSTR_TYPE_LUI   = 7'b0110111, // U load upper immediate
+      INSTR_TYPE_AUIPC = 7'b0010111, // U add upper immediate PC
+      INSTR_TYPE_JAL   = 7'b1101111, // J jump and link
+      INSTR_TYPE_JALR  = 7'b1100111, // I jump and link register
+      INSTR_TYPE_BR    = 7'b1100011, // B branch
+      INSTR_TYPE_LD    = 7'b0000011, // I load
+      INSTR_TYPE_ST    = 7'b0100011, // S store
+      INSTR_TYPE_IMM   = 7'b0010011, // I arith ops with register/immediate operands
+      INSTR_TYPE_REG   = 7'b0110011, // R arith ops with register operands
       INSTR_TYPE_CSR   = 7'b1110011  // I control and status register
   } opcode_t;
 
@@ -18,21 +25,37 @@ package riscv_types;
     MEM_OP_NONE
   } mem_op_t;
 
-  typedef enum logic [1:0] {
-    REG_IMM_OFFSET,
-    PC_IMM_OFFSET,
-    OFFSET_NONE
-  } brjmp_op_t;
+  typedef enum logic [2:0] {
+    BEQ  = 0,
+    BNE  = 1,
+    BLT  = 2,
+    BGE  = 3,
+    BLTU = 4,
+    BGEU = 5
+  } br_op_t;
+
 
+  //------------
+  // ALU Control
+  //------------
   typedef enum logic [1:0] {
     RS1,
     PC,
-    OP_NONE
-  } aluSelOp1_t;
+    ZERO
+  } alu_sel_op_1_t;
 
   typedef enum logic {
     RS2,
     IMM
-  } aluSelOp2_t;
+  } alu_sel_op_2_t;
+
+  typedef struct packed {
+    logic                  func7;
+    logic [2:0]            func3;
+    logic [WORD_WIDTH-1:0] immediate;
+
+    alu_sel_op_1_t         rs1Sel;
+    alu_sel_op_2_t         rs2Sel;
+  } alu_op_t;
 
 endpackage