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authorJoshua Yun <joshua@joshuayun.com>2025-03-15 23:09:39 -0500
committerJoshua Yun <joshua@joshuayun.com>2025-03-15 23:09:39 -0500
commit6bd9f4f7ab48576d3fda98bef915162a7436866d (patch)
treea0af72467af1020f9e492b177e2d95ed8998d1dc /core/rtl/decode.sv
parent59fd8c25ee1452452cb564d6fe4163b7a9394aef (diff)
downloadriscv-processor-6bd9f4f7ab48576d3fda98bef915162a7436866d.tar.gz
feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64
Diffstat (limited to 'core/rtl/decode.sv')
-rw-r--r--core/rtl/decode.sv34
1 files changed, 34 insertions, 0 deletions
diff --git a/core/rtl/decode.sv b/core/rtl/decode.sv
new file mode 100644
index 0000000..e337e11
--- /dev/null
+++ b/core/rtl/decode.sv
@@ -0,0 +1,34 @@
+module decode
+import riscv_types::*;
+#(
+ )
+ (
+ input logic clk,
+ input logic rst_l,
+
+ // I-MEM Interface
+ input logic [31:0] imem_id_instr_ID
+ );
+
+opcode_t instrOpCode_ID;
+
+assign instrOpCode_ID = opcode_t'(imem_id_instr_ID[6:0]);
+
+always_ff @(posedge clk) begin
+ $display("Instruction: %x", imem_id_instr_ID);
+ case (instrOpCode_ID)
+ INSTR_TYPE_LUI: begin $display("Instr type: LUI"); end
+ INSTR_TYPE_AUIPC: begin $display("Instr type: AUIPC"); end
+ INSTR_TYPE_JAL: begin $display("Instr type: JAL"); end
+ INSTR_TYPE_JALR: begin $display("Instr type: JALR"); end
+ INSTR_TYPE_BR: begin $display("Instr type: BR"); end
+ INSTR_TYPE_LD: begin $display("Instr type: LD"); end
+ INSTR_TYPE_ST: begin $display("Instr type: ST"); end
+ INSTR_TYPE_IMM: begin $display("Instr type: IMM"); end
+ INSTR_TYPE_REG: begin $display("Instr type: REG"); end
+ INSTR_TYPE_CSR: begin $display("Instr type: CSR"); end
+ default: begin $display("Instr type: Unknown"); end
+ endcase
+end
+
+endmodule