feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64

1 files changed, 8 insertions, 6 deletions

diff --git a/core/rtl/fetch.sv b/core/rtl/fetch.sv
index 7cbff6a..d2b5ed0 100644
--- a/core/rtl/fetch.sv
+++ b/core/rtl/fetch.sv
@@ -1,20 +1,22 @@
 module fetch
+import riscv_types::*;
 (
   input  logic clk,
   input  logic rst_l,
 
   // IMEM interface
-  output logic [63:0] if_imem_addr_IF
+  output logic [31:0] if_imem_addr_IF
 );
 
-logic [63:0] pc_IF;
-logic [63:0] pcNxt_IF;
+logic [31:0] pc_IF;
+logic [31:0] pcNxt_IF;
 
-assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, truncate addresses to be 64 bit aligned?
+assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, addresses are always 32 bit aligned
+                                // TODO: Find out if 32 is the best fetching width vs 16
 
 // Program Counter (PC)
-assign pcNxt_IF = pc_IF + 64'd4;
+assign pcNxt_IF = pc_IF + 32'd4;
 
-AFFR #(.WIDTH(64)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) );
+AFFR #(.WIDTH(32)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) );
 
 endmodule